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| Fault-tolerant power supply system |
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Circuit configuration for protecting the operation of a computer-controlled apparatus
| Details |
Inventors: Graf, Friedrich; Niedermeier, Ernst; Staerker, Klaus; Flaig, Jorg;
Assignee: Siemens Aktiengesellschaft (Munich, DE)
Primary Examiner: Harvey; Jack B.
Assistant Examiner: Auve; Glenn A.
Attorney, Agent or Firm: Lerner; Herbert L., Greenberg; Laurence A.
A control unit is controlled by a computer having a reset input. A circuit configuration protects the operation of the control unit by placing a signal at the reset input for restarting the computer in the event of a malfunction. The circuit configuration includes a first register into which a predetermined bit pattern is written in read-only fashion; a second check register in which a single defined bit is set at a time after individual program routines have been executed; a counter timer; and a comparator connected to the first register, to the second check register and to the counter timer, for comparing contents of the second check register with contents of the first register and outputting a reload signal for reloading the counter timer if the contents match. |
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DETAILED DESCRIPTION With the foregoing and other objects in view there is provided, in accordance with the invention, in a control unit being controlled by a computer having a reset input, a circuit configuration for protecting the operation of the control unit by placing a signal at the reset input for restarting the computer in the event of a malfunction, comprising a first register into which a predetermined bit pattern is written in read-only fashion; a second check register in which a single defined bit is set at a time after individual program routines have been executed; a counter timer; and a comparator connected to the first register, to the second check register and to the counter timer, for comparing contents of the second check register with contents of the first register and outputting a reload signal for reloading the counter timer if the contents coincide or correspond.
In accordance with another feature of the invention, there are provided means for allowing writing into the second check register only in increasing order.
In accordance with a further feature of the invention, the first register is written into by the computer and has contents that are loaded into the counter timer.
In accordance with an added feature of the invention, the counter timer is a downward counter for outputting a reset signal when a value 0 is attained.
In accordance with an additional feature of the invention, there is provided a reset circuit having a first input receiving an external reset signal, a second input receiving the reset signal of the counter timer, and a third input receiving the reload signal.
In accordance with yet another feature of the invention, the reset circuit has a first output from which a reset signal is fed to the computer when one of the reset signals is present at one of the first and second inputs of the reset circuit, and the reset circuit has a second output for supplying a blocking signal for putting an apparatus into a safe state.
In accordance with yet a further feature of the invention, the reset circuit has an output for supplying an enable signal enabling the control unit to control an apparatus, when the reload signal is present at the third input of the reset circuit
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