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Complementary logic input parallel (CLIP) logic circuit family
| Details |
Inventors: Vinal, Albert W.;
Assignee: Thunderbird Technologies, Inc. (Research Triange Park, NC)
Primary Examiner: Westin; Edward P.
Assistant Examiner: Sanders; Andrew
Attorney, Agent or Firm: Bell, Seltzer, Park & Gibson
A high speed low Capacitance Complementary Logic Input Parallel (CLIP) logic family includes an FET driving stage, a complementary FET inverter, and at least one gating FET. The dimensions of the gating FET are controlled relative to the dimensions of the driving stage FETs to provide a high speed logic circuit. AND and OR CLIP logic circuits may be provided. A clocked CLIP logic circuit may be provided by adding a clocking FET. A latching clocked CLIP logic circuit may also be provided by adding a latching FET. In the latching clocked CLIP logic circuit, the gate output is latched so that it does not change during the clock period regardless of changes in the logic inputs of the circuit. The speed of the CLIP logic circuits may be further increased by including germanium in the channel of its P-channel FETs to thereby increase carrier mobility in the P-channel FETs. The N-channel FETs are free of germanium. The internal capacitance of the CLIP logic circuits is also decreased by using common diffusion regions in the integrated circuit for pairs of driving stage FETs. Common source and/or common drain diffusion regions may be used. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide a high speed complementary all-parallel FET logic circuit family.
It is another object of the present invention to provide a high speed complementary all-parallel FET logic family which exhibits minimum delay.
It is yet another object of the invention to provide a high speed complementary all-parallel FET logic family, the performance of which is not limited by the inherently lower saturation current and carrier mobility of P-channel FET devices.
It is still another object of the present invention to provide a high speed complementary all-parallel FET logic family which exhibits low internal capacitance so that large numbers of logic inputs may be handled by a single gate.
These and other objects are provided according to the present invention by a Complementary Logic Input Parallel ("CLIP") logic circuit family, which includes a driving stage having at least one FET of a first conductivity type, with each FET having at least one control electrode for receiving logical input signals.
The driving stage FETs are connected between a common output and a first potential level.
A complementary FET inverter, comprising a pair of complementary FETs, is serially connected between the first potential level and a second potential level, with the input of the complementary inverter being connected to the common output.
According to the invention, at least one gating FET of second conductivity type is provided, with the gating FET being connected between the second potential level and the common input.
The control electrode of the gating FET is connected to the control electrode of one of the driving stage FETs.
The dimensions of the gating FETs are controlled relative to the dimensions of the driving stage FETs to provide a high speed logic circuit.
In particular, the ratio of the channel width of the gating FETs to the channel width of the driving stage FETs is substantially equal to the ratio of the square channel saturation current of the driving stage FETs to the square channel saturation current of the gating FETs times the ratio of the channel length of the gating FETs to the channel length of the driving stage FETs times the number of gating FETs, divided by 2
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CPUs 
