 Programmable logic array integrated circuits |
| The present invention provides programmable logic array integrated circuits in which signal ... |
|
| Electric socket adapter |
| In accordance with this invention, a socket adapter having any combination of a rectifier, ... |
|
| Memory arbitration between timekeeping circuitry and general purpose computer |
| It is, therefore, an object of this invention to provide a method and circuitry for arbitrating ... |
|
| Transition for electrical apparatus |
| I claim: 1. An electrical transition comprising: a) a nonconductive base having extending upwardly ... |
|
| Microprogram control system |
| The present invention intends to eliminate the above disadvantages and has for its object to ... |
|
| Data bank priority system |
| OF THE PREFERRED EMBODIMENT Turning now to the drawings, there is shown in FIG. 1 part of a data ... |
|
| Integrated circuit device having a memory and majority logic |
| I claim: 1. An integrated circuit device comprising: a memory having at least first, second and ... |
|
| Logic circuit system with latch circuits for reliable scan-path testing |
| It is, therefore, a primary object of the present invention to provide an IC logic circuit having ... |
|
|
Computer-implemented method of optimizing a time multiplexed programmable logic device
| Details |
Inventors: Trimberger, Stephen M.;
Assignee: Xilinx, Inc. (San Jose, CA)
Primary Examiner: Trans; Vincent N.
Assistant Examiner: Frejd; Russell W.
Attorney, Agent or Firm: Harms; Jeanette S., Klivans; Norman R. Skjerven Morrill MacPherson Franklin & Friel
A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method. The step of ordering alternatively includes identifying the LUTs with the earliest latest-possible schedule, identifying the LUTs having input nets in which all LUTs are already scheduled, identifying the LUTs that include a pin on a net that has had at least one of its destination instances scheduled, identifying the LUTs that will complete a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs, or identifying the LUTs that include a pin on a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs. In another embodiment, the method includes the first three steps, then further includes determining whether the number of selected LUTs is equal to M, wherein M is the number of real LUTs in the programmable logic device. The steps of labeling and removing are repeated until the number of selected LUTs is equal to M. Then, the M LUTs with the current micro cycle number are labelled and removed from the list. The next micro cycle is then identified. If labelled LUTs exist, then all steps are repeated. |
|
DETAILED DESCRIPTION In accordance with the present invention, a computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method.
The step of ordering alternatively includes identifying the LUTs with the earliest latest-possible schedule, identifying the LUTs having input nets in which all LUTs are already scheduled, identifying the LUTs that include a pin on a net that has had at least one of its destination instances scheduled, identifying the LUTs that will complete a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs, or identifying the LUTs that include a pin on a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs.
In another embodiment of the present invention, the method includes the first three steps, then further includes determining whether the number of selected LUTs is equal to M, wherein M is the number of real LUTs in the programmable logic device.
The steps of labeling and removing are repeated until the number of selected LUTs is equal to M.
Then, the M LUTs with the current micro cycle number are labelled and removed from the list.
The next micro cycle is then identified.
If labelled LUTs exist, then all steps are repeated.
|
| Related patents |
|
|
Power-up circuit for field programmable gate arrays
FIG. 1 is an illustration of a portion of a prior art device 100 showing a first logic module 101 and a second logic module 102 that have been interconnected by ...
|
|
|
Method and structure for loading data into several IC devices
The present invention provides a method and structure for loading data into a plurality of integrated circuit devices. The devices are tied together as a series array ...
|
|
|
Method and apparatus for calculating an error detecting code block in a disk drive controller
OF THE DRAWINGS FIG. 1 is a block diagram of a computer system including a disk drive subsystem according to the present invention. In FIG. 1, a plurality of N central ...
|
|
|
Semiconductor junction antifuse circuit
A junction antifuse is formed by one or more reverse-biased semiconductor junctions. In one embodiment of the invention, two n+ regions are spaced apart in a p-type ...
|
|
|
Programmable logic array intergrated circuit devices
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit ...
|
|
|
Scalable multiple level tab oriented interconnect architecture
An improved field programmable gate array (FPGA) is provided which includes tab network connectors for interfacing groups of logic cells with lower levels of ...
|
|
|
Programming architecture for a programmable integrated circuit employing antifuses
OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing how FIGS. 1A, 1Ba, 1Bb, 1Bc, 1C, 1D, 1E, 1Fa, 1Fb, 1Fc, 1G, 1H, 1I, 1Ja, 1Jb, 1Jc, 1K, 1L, 1M, 1Na, 1Nb, 1Nc, 10...
|
|
|
High density programmable logic device
The programmable logic device (PLD) of this invention is a high density segmented PAL-like device which gives an optimum balance between functionality, silicon die size, ...
|
|
|
Dedicated local line interconnect layout
An electrical connection arrangement for a programmable integrated circuit is described. An electrical device is disposed proximate to a vertical arranged longline which ...
|
|
|
Tile-based modular routing resources for high density programmable logic device
The present invention relates to signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a ...
|
|
|
CPUs 
