Data acquisition system and method with a selectable sampling rate

DETAILED DESCRIPTION The present invention comprises an improved data acquisition system for digitizing and storing analog data at a selectable sample rate.
The analog data signal is first digitized at a rate defined by a high-frequency clock signal.
A decelerator collects every N digital data samples and outputs the samples to N memory partitions at a reduced rate equal to the original clock frequency divided by N.
The N memory partitions are further configured to receive N store-enable signals corresponding to each of the N digital data samples.
Each of the N store-enable signals determines whether a memory partition will store the corresponding digital data sample.
By choosing an appropriate pattern for the N store-enable signals, only a portion of the generated digital data signals is stored in memory.
This results in a selectable effective sampling rate for the analog data.
Broadly speaking, the present invention contemplates an analog-to-digital converter (ADC) configured to receive an analog data signal and a first clock signal having a first clock frequency F1.
The ADC is operable to sample the analog data at the first clock frequency F1 and convert samples of the analog data into digital data samples.
In a preferred embodiment, the analog data signal is sampled at 1 GHz with each sample being 8 bits long.
The system includes a decelerator which includes an input coupled to the ADC and is configured to receive the digital data samples.
The decelerator is operable to store every N of the digital data samples in data buffers within the decelerator.
The decelerator further includes N outputs for outputting the N digital data samples in a parallel fashion.
The N digital data samples are output at a second clock frequency F2=F1/N.
The decelerator repetitively operates to receive and store N digital data samples and output the N digital data samples in a parallel fashion.
In a preferred embodiment, the decelerator may comprise 8 outputs, outputting data at a rate of 1 GHz/8=125 MHz.
A memory is coupled to the decelerator and is configured to receive the N output digital data samples