 Computer-printable adhesive note system |
| It is an object of the present invention to provide a computer-printable adhesive note system which ... |
|
| Method and apparatus for recording characters |
| It is an object of the present invention to specify a method and an apparatus for picture-element-... |
|
| Pick function implementation in a parallel processing system |
| We claim: 1. In a graphics system in which a predetermined number of pixels representing a fragment ... |
|
| Method of multiple CPU logic simulation |
| The present invention provides a method of simulating the hardware design of a multiple CPU ... |
|
| Programmable logic device |
| I claim: 1. A method of operating a computing element to compile a set of state-machine states in ... |
|
| Programmable multiplexing input/output port |
| The present invention discloses an input/output buffer design for FPGAs and other programmable ... |
|
| Portable terminal which reliably confirms program installation |
| Therefore, a primary object of the present invention is to provide a portable terminal to be used ... |
|
| Boundary drawing and area filling logic for a display system |
| We claim: 1. A computer graphics system having display logic comprising: a destination bit map ... |
|
| Data acquisition system using non-linear digitization intervals |
| Accordingly, it is a general object of the present invention to provide an improved data ... |
|
| High speed data acquisition system and method |
| OF THE PREFERRED EMBODIMENTS Reference will now be made to the drawings wherein like structures ... |
|
|
Decimation filter
| Details |
Inventors: Saramaki, Tapio; Ritoniemi, Tapani; Eerola, Ville; Husu, Timo; Pajarre, Eero; Ingalsuo, Seppo;
Assignee:
Primary Examiner: Elmore; Reba I.
Assistant Examiner: Patel; Ramesh
Attorney, Agent or Firm: Dennison, Meserole, Pollack & Scheiner
The invention relates to a decimation filter comprising a direct cascade arrangement of digital first order and second order integration and derivation stages (22, 23, 25, 27) and a decimation stage. The decimation filter structure of the invention comprises additional branches (28, 29, 30, 31) for shifting the location of the attenuation zeros of the decimation filter and thereby reducing the order M and the number of structural elements M of the required filter. |
|
DETAILED DESCRIPTION This is achieved with the decimation filter set forth in the preamble, which in accordance with the invention is characterized in that the decimation filter further comprises M.
sub.
2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to the M.
sub.
1 -stage integrator and the output of the derivation stage of the i:th second stage subsequent to the decimation block in the main branch a signal processing branch (realizes the (i+K.
sup.
* i) clock cycle delay at sampling frequency F.
sub.
s and the coefficient) is connected comprising, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F.
sub.
s of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F.
sub.
s /K, and a scaling element having a scaling factor .
alpha.
.
sub.
i where i=1,2,3, .
.
.
, M.
sub.
2.
The present invention also relates to another decimation filter as set forth in the preamble, which is characterized in that the decimation filter comprises M.
sub.
2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to M.
sub.
1 and the output of the main branch a signal processing branch is connected comprising, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F.
sub.
s of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F.
sub.
s /K, a (M.
sub.
1 +2(M.
sub.
2 -i))-stage derivation block, and a scaling element having a scaling factor .
alpha.
.
sub.
i where i=1,2,3, .
.
.
, M.
sub.
2.
The decimation filter structure according to the invention comprises additional branches for shifting the location of the attenuation zeros of the decimation filter and thereby reducing the order M and the number of structural elements M of the required filter
|
|
CPUs 
