Demodulation logic unit adaptable to multiple data protocols

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Generally this disclosure deals with a data demodulation logic unit that has improved power consumption and enhanced data demodulation capabilities.
This data demodulation logic unit includes an arithmetic logic unit that has been architecturally optimized for data demodulation requirements and a hardware based state machine that is advantageously arranged to operate in a mode that selectively corresponds to one of a plurality of possible data modulation protocols.
The instant invention will be further explained by reference to the Figures, in which FIG.
1 is a data receiver (100).
The data receiver (100) is coupled to an antenna (101) and is arranged and constructed to receive a radio frequency (RF) signal that includes data modulation in accordance with one of a plurality of data protocols.
The data receiver (100) includes a receiver (103) coupled to a decoder (105) at a decoder input (107).
The receiver (103) converts the RF signal to a base band signal at a decoder input (107) and the decoder (105) processes, as further explained below, this base band signal to provide data at an output (109).
The decoder (105), shown in FIG.
2 and preferably embodied in a semi-custom application specific integrated circuit (ASIC), includes an analog-to-digital (A/D) converter (201) which converts the base band signal at the decoder input (107) to sampled digital values or digital words at an output (202).
A timing adjuster (217) controls the timing of the A/D converter (201) through a set of control signals (221) as indicated at an input (219).
The sampled digital values (202) are coupled to and processed by a digital filter (203) which provides filtered sampled data.
The filtered sampled data is coupled to an input (204) of a data demodulation logic unit (200).
The data demodulation logic unit (200) is the heart of the decoder (105) and the data receiver (100) and includes an arithmetic logic unit (ALU) (205) and a state machine (209).
The ALU (205) includes an input, depicted as the input (204), an output (206), and a timing output coupled to the input (219) of the timing adjuster (217), and is controllably operable to convert a base band signal, specifically the filtered base band signal, at the input (204) to a demodulated data signal at the output (206)