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 Digital sample rate reduction system

Details
Inventors: Willis, Donald H.;
Assignee: RCA Corporation (Princeton, NJ)
Primary Examiner: Heyman; John S.
Assistant Examiner: Ohralik; K.
Attorney, Agent or Firm: Rasmussen; Paul J., Herrmann; Eric P., Kulkarni; Dilip A.

A digital sample rate reduction apparatus receives an input signal occurring at a given sample rate and produces an output signal occurring at a rate which is two-thirds the input sample rate. One half of the output samples are interpolated samples and the other half are original input samples.

DETAILED DESCRIPTION FIG.
1 shows the subject digital sample rate reduction apparatus 100.
FIG.
5 illustrates the associated waveforms.
In respect of FIG.
1, it will be noted that the input and output samples are multibit binary samples of parallel bits (e.
g.
, 8 bits), and that the interconnecting lines A-G, latches, etc.
, are all multibit parallel arrangements.
In connection with FIG.
5, it will be noted that the Fsc and 4 Fsc clocks are system clocks in a 4 Fsc sampling system, and the invention circuitry develops the remaining clocks--(8/3) Fsc, (8/3) Fsc, (8/6) Fsc and (8/6) F'sc from the system clocks.
The letter A in FIG.
5 indicates an input sample sequence in a 4 Fsc sampling system.
The dots in the sample sequence A indicate the points at which the respective samples are taken.
The sample values are, however, present on the line A in FIG.
1 for the entire 4 Fsc clock period.
The interconnecting lines A-G in FIG.
1 correspond to the sequences A-G in FIG.
5.
The instant sample rate reduction apparatus 100 produces an output sample sequence G having a sample rate which is two-thirds of the input sample rate of 4 Fsc.
The subject sample rate reduction apparatus 100 includes a set of three latches 102, 104 and 106 connected to each other in series.
The input sample sequence occurring at the 4 Fsc rate, and available at an input terminal 108, is clocked through the latches 102, 104 and 106, acting as a three-stage shift register delay line, in response to the associated 4 Fsc clock pulses.
The outputs of the latches 102, 104 and 106 on the associated lines B, C and D are respectively identified by the sequences B, C and D in FIG.
5.
As the input sample sequence is clocked through the latches 102, 104 and 106, the successive sets of four input samples are made available, simultaneously, to a four input cubic interpolator 110 on lines A, B, C and D respectively.
The cubic interpolator 110 produces on the output line E a stream of interpolated samples, indicated by the letter E in FIG.
5, in accordance with an equation I=-(1/16)X



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