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 Digital signal detector

Details
Inventors: Sumner, Terence E.; Backof, Jr., Charles A.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Bookbinder; Marc E.
Assistant Examiner: Durigon; Peter
Attorney, Agent or Firm: Hackbart; Rolland R., Gillman; James W.

A digital signal detector is disclosed that detects a serial bit stream transmitted at a predetermined bit frequency. Bit transitions are totallized in a counter over a predetermined time interval. Bit transitions occurring during a good window interval increment the totallized count by one. Bit transitions occurring during a bad window interval decrement the totallized count by one. Bit transitions occurring during a marginal window interval, situated between the good and bad window intervals, do not affect the totallized count. If the counter reaches a predetermined count during the time interval, a detect signal is provided indicating that the digital signal has been detected. The counter can be further loaded with a threshold count for tailoring the digital signal detector for operation at a particular signal-to-noise ratio. Periodic signals that have frequencies that are submultiples of the bit frequency are detected by correlating the digital signal between two predetermined stages of a shift register. The digital signal detector may provide a detector output signal when both the digital signal is detected and periodic signals having submultiple frequencies are not present.

DETAILED DESCRIPTION It is an object of the present invention to provide an improved detector for digital signals transmitted in serial bit streams at a predetermined bit frequency by a clock signal.
It is another object of the present invention to provide an improved digital signal detector that has a variable threshold for adjusting the detector sensitivity.
It is a further object of the present invention to provide an improved digital signal detector that is substantially immune to periodic signals having submultiple frequencies of the bit frequency.
It is yet a further object of the present invention to provide an improved digital signal detector that provides for hysteresis in the detector threshold.
In practicing the invention, there is provided a detector for detecting digital signals transmitted in serial bit streams at a predetermined bit frequency by a clock signal and providing an indication signal that the digital signal is present.
The detector includes a first counter responsive to the clock signal for providing a reset pulse signal at the end of each N bit interval, where N is an integer.
A transition detector provides a transition pulse signal for each change in logical state between successive bits of the digital signal.
A window generator repetitively generates a plurality of window signals during each bit interval.
Each of the window signals has a corresponding weighted value associated with it.
The weighted value for each window signal is predeterminedly related to the probability of bit transitions occurring in the interval of the respective window signal.
For example, the weighted value associated with a window signal whose interval is located in synchronism with the expected bit transitions will be relatively high, as compared to the weighted value for a window signal whose interval is located in quadrature with the expected bit transitions.
A second counter provides for each N bit interval a totallized count formed by totallizing for each transition pulse signal, the weighted value corresponding to the window signal during which the respective transition pulse signal occurs



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