Digital synthesis technique for pulses having predetermined time and frequency domain characteristics

DETAILED DESCRIPTION In FIG.
1, an illustrative embodiment of the invention performs the digital synthesis technique to produce an analog output signal ideally suited for the radio transmission of spectrally shapd four-level pulse code modulated (PCM) digital signals.
Each of these four nominal levels corresponds to a particular combination of two successive bits designated at data input 11 as an "AB" pair.
The basic configuration of the circuit of FIG.
1 includes accessor 12 which takes sequential combinations of bits in the incoming data signals to provide successive parallel addresses for memory 13.
Connected to the output of memory 13 is sequencer 14 which alternates between the two sections (ROM 13-1 and ROM 13-2) of memory 13 to provide an appropriate sequence of parallel groups of digitally coded bits for application to converter 16 via logic shifter 17.
Logic shifter 17 is required only because sequencer 14 uses TTL devices and converter 16 uses ECL devices.
Since the ECL logic is balanced and relatively low impedance, it provides a measure of noise immunity.
Converter 16 produces a particular form of analog signal corresponding to a spectrally shaped fourlevel PCM digital signal at the baud rate associated with the transmission system.
Accessor 12 initially includes serial-to-parallel converter 21 which has two outputs, one feeding shift register 22 and the other feeding shift register 23.
Shift registers 22 and 23 each include five cells of digital delay elements, which may be viewed as a tapped delay line providing the memory required to establish past, present and future bit combinations or AB bit pairs which together as a parallel group provides each address for memory 13.
The data input of accessor 12 constitutes independent coded values which, when viewed in succession, can form a random sequence.
The random aspect of this sequence is significant since in prior signal synthesis applications a periodic signal is generated and the address sequentially calls up information from memory