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Management method for a multiprocessor system
It is an object of the present invention to solve the above problems. The present invention provides a multiprocessor system including at least one supervisor to which a ...
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CMOS output buffer circuit with improved ground bounce
Accordingly, it is a general object of the present invention to provide a CMOS output buffer circuit with a significant reduction in ground bounce which is relatively ...
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Selectable edge rate CMOS output buffer circuit
I claim: 1. A CMOS tristate output buffer circuit having an output pullup driver (P1) and an output pulldown driver (N1) coupled to an output (V.sub.OUT), a pullup ...
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State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections
The above and other objects of the present invention are achieved in a preferred embodiment of a unit which includes a state machine for defining sequential states used ...
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Software controlled power shutdown in an integrated circuit
An object of the invention is control of power shutdown within an integrated circuit without the use of dedicated package pins. A feature of the invention is the use of ...
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Integrated circuit with a low-power mode and clock amplifier circuit for same
Accordingly, there is provided, in one form, an integrated circuit with a low-power mode, comprising an inverter portion, a resistor, a logic portion, and an internal ...
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Low power clocking apparatus and method
A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via ...
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On chip monitor
Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 1. In an integrated digital logic circuit chip having an LSSD ...
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Parallel data transmission unit using byte error correcting code
An object of the invention, therefore, is to overcome the problems existing in the prior art and to provide a parallel data transmission unit in which an error ...
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Semiconductor memory device with redundancy structure suppressing power consumption
OF THE PRESENT INVENTION Referring to FIG. 2, the difference between the structure of FIGS. 1 and 2 is located in fuses. Fuses A and B, serving as cutting means, are ...
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