Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home CPUs Dither-signal-insertion-inversely-proportional-to-signal-level-in-delta-sigma-modulators

 High precision capacitance bridge
It is an object of this invention to measure impedance, and particularly capacitance, to extremely ...


 Split programmable logic array
The subject invention relates to an improved programmable logic array for producing a particular ...


 Dynamic re-programmable PLA
An advantage of the present invention resides in the provision of a unique design that is readily ...


 Multiple array customizable logic device
The present invention provides an integrated circuit having customizable logic, comprising a first ...


 Secure integrated circuit chip with conductive shield
We claim: 1. An integrated circuit chip containing a secure area in which secure data is processed ...


 High speed state machine
Accordingly, it is an object of the present invention to provide a state machine in which the ...


 Programmable integrated circuit micro-sequencer device
OF THE PREFERRED EMBODIMENTS A preferred implementation of the basic building block of the present ...


 Eprom low voltage sense amplifier
We claim: 1. A low voltage sense amplifier for an EPROM memory transistor comprising a low voltage ...


 Recirculating memory with plural input-output taps
It is an object of this invention to provide a random access memory having serially coupled memory ...


 Semiconductor memory device comprising address holding flip-flop
This invention is intended to solve the above problem by providing a semiconductor memory device ...


 Dither signal insertion inversely proportional to signal level in delta-sigma modulators

Details
Inventors: Korkala, Vesa;
Assignee: Nokia Corporation (Espoo, FI)
Primary Examiner: Williams; Howard L.
Assistant Examiner:
Attorney, Agent or Firm: Harrington & Smith, LLP

A method is disclosed to operate a sigma-delta modulator of a type that includes a quantizer. The method has steps of (a) sampling an amplitude of an input signal to the sigma-delta modulator; and (b) controlling the switching of a capacitance bank in accordance with the sampled amplitude of the input signal for generating a dither signal at an input of the quantizer. The dither signal is generated to have a pseudorandom amplitude that is inversely proportional to the sampled amplitude of the input signal. The step of controlling and generating operates a linear feedback shift register to switch individual ones of a plurality of capacitances of the bank of capacitances in and out of a capacitance network. In one embodiment the step of operating the at least one linear feedback shift register turns a linear feedback shift register clock signal on and off as a function of the amplitude of the input signal. In one embodiment the step of sampling operates at least one window detector, and the dither signal is turned off and on depending on a relationship between the amplitude of the input signal and voltage thresholds of the window detector. In another embodiment the step of sampling operates a rectifier that rectifies the input signal to provide a rectified output signal, and the step of controlling and generating pseudorandomly applies the rectified output signal to the bank of capacitances for controlling an amount of current that is transferred between the input of the quantizer and the bank of capacitances.

DETAILED DESCRIPTION The foregoing and other problems are overcome and the foregoing objects and advantages are realized by methods and apparatus in accordance with embodiments of this invention.
The teachings of this invention provide embodiments of low complexity, single-bit SD modulators that employ a dither signal having an amplitude that is a function of the amplitude of the input signal to the SD modulator.
The teachings of this invention apply as well to multi-bit SD modulators.
In these embodiments pseudorandom noise is added to an input of a SD modulator quantizer as a dither signal, and the amplitude of the pseudorandom noise is controlled in such a manner as to be inversely proportional to the amplitude of the input signal, i.
e.
, the amplitude of the dither signal is smallest when the amplitude of the input signal is largest and vice versa.
In the presently preferred embodiments at least one linear feedback shift register (LFSR) is used to generate a pseudorandom code sequence that in turn is used to control the switching of voltage potentials to inputs of banks of voltage variable capacitances coupled to input nodes of the quantizer.
The variation in capacitance at the input nodes of the quantizer generates voltage transitions in the quantizer input signal, thereby dithering the input signal to the quantizer.
In a further embodiment of this invention embodiment of this invention the instantaneous amplitude of the input signal is quantized with at least one low complexity window detector which controls the clock signal to the at least one LFSR.
A method is disclosed to operate a sigma-delta modulator of a type that includes a quantizer.
The method has steps of (a) sampling an amplitude of an input signal to the sigma-delta modulator; and (b) controlling the switching of a capacitance bank in accordance with the sampled amplitude of the input signal for generating a dither signal at an input of the quantizer.
The dither signal is generated to have a pseudorandom amplitude that is inversely proportional to the sampled amplitude of the input signal



Related patents
  Model train control system
OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a model train control system 10 includes a communications transport 12 interconnecting a client program 14 and a ...
  Control, sound, and operating system for model trains
The present invention provides a model train operating, sound and control system that provides a user with operating realism beyond that found in prior art systems. The ...
  Control, sound, and operating system for model trains
The present invention provides a model train operating, sound and control system that provides a user with operating realism beyond that found in prior art systems. The ...
  Integrated circuit testing device with dual purpose analog and digital channels
What is claimed is: 1. An apparatus for performing tests on integrated circuits, each integrated circuit having a plurality of terminals, wherein each of said tests is ...
  Equalization system for modems in a polled arrangement
OF THE PREFERRED EMBODIMENTS In FIG. 1, a data processor 1 is connected to a plurality of remote modems 3a, 3b, 3c . . . 3n via a central modem 5. Each of the remote ...
  Latched fedback memory finite-state-engine
The present invention has been contemplated to overcome the foregoing deficiencies and meet the above described needs. The latched fedback-memory finite-state-engine of ...
  Integrated sample and hold circuit
The present invention overcomes this inherent inapplicability of bipolar semiconductor devices by providing a high speed sample and hold circuit comprising bipolar ...
  Digital data processing system with asynchronous sensing units
In order to overcome the aforementioned drawbacks, the invention provides a digital data processing system of the type which can be used to protect a large-scale analog ...
  Cable tester for multipair cables
In elaborating on the particulars of the illustrative embodiment, it is helpful to visualize and discuss a layout of the complete system in an overview fashion. A...
  Apparatus and method of testing CML circuits
A test apparatus for CML integrated circuits is shown herein. The apparatus has a test unit which is capable of determining differences in the pulses and various ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved