Dynamic re-programmable PLA

DETAILED DESCRIPTION An advantage of the present invention resides in the provision of a unique design that is readily adaptable to standard MOS (metal oxide semiconductor) fabrication techniques.
Another advantage of this invention is the provision of a PLA design that is readily programmable or re-programmable as required, and requires reduced semiconductor chip area ("real estate").
A programmable logic array is provided which has an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines and m bit lines coupling the AND or OR arrays, wherein the array comprises new and improved random access AND or OR arrays.
The AND array includes n.
times.
m cells wherein each cell has first and second transistor means coupled in series between one of the term lines and a reference potential.
Each cell includes a charge storage element coupled to the control element of the first transistor means and one of the n input terminals is coupled to the control element of the second transistor means.
The OR array includes m.
times.
k cells wherein each cell has third and fourth transistor means coupled in series between one of said output lines and a reference potential.
Each of the OR array cells also includes a charge storage element coupled to the control element of the third transistor means and one of the m term lines is coupled to the control element of the fourth transistor means.
Refresh logic is coupled to the bit lines for periodically restoring the charge on the charge storage elements.