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Apparatus and method for product term allocation in programmable logic |
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Level converter circuit for converting ECL-level input signals |
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Logic gates with controllable time delay |
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Programmable logic cell and array |
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Output logic macrocell with enhanced functional capabilities |
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Graphics system including an output buffer circuit with controlled Miller effect capacitance |
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Safestore frame implementation in a central processor |
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Refresh control for dynamic memory in multiple processor system |
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System and method for providing a fault tolerant computer program runtime support environment |
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Dynamically programmable logic circuits
| Details |
Inventors: Suarez, Ricardo; Chang, Oscar; Adam, Vladimir;
Assignee: Instituto Venezolano de Investigaciones Cientificas (IVIC) (VE)
Primary Examiner: Dixon; Harold A.
Assistant Examiner:
Attorney, Agent or Firm: Browdy and Neimark
A programmable logic circuit is formed by at least one gate. The gate is formed by four logic circuits, one being a first exclusive NOR circuit having a first input, a second input and an output. A second exclusive NOR circuit having a first input, a second input and output is provided, the first input of the second exclusive NOR circuit being coupled to the first input of said first exclusive NOR circuit. An AND circuit having a first input, a second input and an output is also provided. The first input of the AND circuit is coupled to the output of the first exclusive NOR circuit and the second input of the AND circuit means is coupled to the output of the second exclusive NOR circuit. A third exclusive NOR circuit having a first input circuit, a second input circuit and an output circuit is provided the first input circuit of the third exclusive NOR circuit is coupled to the output of the AND circuit. The gate can selectively function as an OR, NOR, AND and NAND circuit depending on ONE and ZERO signal levels applied to the respective second inputs of the second and the third exclusive NOR circuits as program variables. One of the variables is applied to the first input of the first exclusive NOR circuit and to the first input of the second exclusive NOR circuit, another variable being applied to the first input of the second exclusive NOR circuit. By connecting the second input of the second exclusive NOR circuit to one of the inputs of the first exclusive NOR circuit, the logic circuit will operate as an exclusive OR or exclusive NOR circuit. |
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DETAILED DESCRIPTION It is an object of the present invention to provide a programmable logic circuit which can perform, under control of program variables, a number of logic functions, using the same components. It is another object of the present invention to provide a programmable logic circuit which can perform a number of logic functions and is itself made of few components. It is a further object of the present invention to provide a programmable logic circuit which, under the control of program variables, can function as an OR, NOR, AND or NAND circuit. It is an additional object of the present invention to provide a programmable logic circuit which can be modified to function as an XOR circuit or an XNOR circuit. It is yet another object of the present invention to provide a programmable logic circuit which can perform a number of logic functions, under the control of program variables, but is itself relatively simple and economical to construct and operate. It is yet a further object of the present invention to provide a programmable logic circuit which can perform a number of logic functions, under the control of program variables and, nevertheless, is efficient in terms of space and time considerations. The foregoing objects, as well as others which are to become clear from the text below, are achieved by a programmable logic circuit which is formed by at least one gate. The gate is formed by four logic circuits, one being a first exclusive NOR circuit having a first input, a second input and an output. A second exclusive NOR circuit having a first input, a second input and output is provided, the first input of the second exclusive NOR circuit being coupled to the first input of said first exclusive NOR circuit. An AND circuit having a first input, a second input and an output is also provided. The first input of the AND circuit is coupled to the output of the first exclusive NOR circuit and the second input of the AND circuit means is coupled to the output of the second exclusive NOR circuit
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