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| High density programmable logic device |
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| Tile-based modular routing resources for high density programmable logic device |
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| Programmable logic array integrated circuits |
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ECL output buffer circuit with improved compensation
| Details |
Inventors: Naghshineh, Kianoosh;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Ouellette; Scott A.
Attorney, Agent or Firm: Chin; Davis
An ECL output buffer circuit for generating a stable predetermined output voltage over power supply, temperature and process variations and having a high speed of operation with low power consumption includes a differential pair formed of first and second input transistors (Q102, Q103), an emitter follower transistor (Q101), a first current source (112), and a second current source (114). The first current source is coupled to the base of the emitter follower transistor for generating a compensating current. The second current source is coupled to the emitters of the first and second input transistors for generating a gate current. |
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DETAILED DESCRIPTION Accordingly, it is a general object of the present invention to provide an improved ECL output buffer circuit which overcomes the disadvantages of the prior art output buffers.
It is an object of the present invention to provide an improved ECL output buffer circuit which has a stable predetermined output voltage swing over power supply, temperature and process variations.
It is another object of the present invention to provide an improved ECL output buffer circuit which has a higher speed of operation with lower power consumption than has been traditionally available.
It is still another object of the present invention to provide an improved ECL output buffer circuit which includes a first current source for generating a compensating current and a second current source for generating a gate current.
It is yet still another object of the present invention to provide an improved ECL output buffer circuit which includes first and second stable bandgap reference voltage generators for controlling accurately and independently the output voltage levels V.
sub.
OH and V.
sub.
OL.
In accordance with these aims and objectives, the present invention is concerned with the provision of an ECL output buffer circuit which provides a stable predetermined output voltage swing over power supply, temperature and process variations and has a high speed of operation with low power consumption.
The ECL output buffer circuit includes a differential pair formed of first and second input transistors, an emitter follower transistor, a first current source, and a second current source.
The first and second input transistors have their emitters connected together.
The first input transistor has its base connected to receive a true input logic signal and its collector connected to a first power supply potential via a first load resistor.
The second input transistor has its base connected to receive a complementary input logic signal and its collector connected to the first power supply potential via a second load resistor
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