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Emitter-coupled logic circuit
| Details |
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Inventors: Tamegaya, Yukio;
Assignee: NEC Corporation (JP)
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Bertelson; David R.
Attorney, Agent or Firm: Laff, Whitesel, Conte & Saret
An emitter-coupled logic circuit, including first to fourth n-p-n transistors, the first transistor having its base connected to a first input signal source and its collector connected to a first supply voltage source, the second transistor having its base connected to a second input signal source and its collector connected to the first supply voltage source, the first and second transistors having their emitters connected to a second supply voltage source via a constant current source, an n-p-n transistor type emitter-follower circuit having an input terminal connected to the collector of the first transistor and its collector connected to the first supply voltage source, a load element connected between the first supply voltage source and the collector of the first or second transistor, the third transistor having its base connected to a reference voltage source and its collector connected to the first supply voltage source, the fourth transistor having its base connected to the base of the first transistor, its collector connected to the emitter of the third transistor and its emitter connected to the second supply voltage source, and a p-n-p transistor type emitter-follower circuit having an input terminal connected to a node between the emitter of the third transistor and the collector of the fourth transistor, the n-p-n and p-n-p transistor type emitter-follower circuits having output terminals connected together to provide an output terminal of the logic circuit. |
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DETAILED DESCRIPTION OF THE PRIOR ART Description will be hereinafter made with reference to FIG.
1 to more clearly show the drawbacks of a prior-art emitter-coupled logic circuit.
In FIG.
1 of the accompanying drawings is shown a conventional emitter-coupled logic circuit which largely consists of a differential amplifier stage 10 and an emitter-follower stage 12 which are connected in parallel between a bus line leading from a high-level supply voltage source 14 and a bus line leading from a low-level supply voltage source 16.
As is customary in the art, the high-level supply voltage source 14 is adapted to supply a high-level supply voltage V.
sub.
CC of, typically, ground level and the low-level supply voltage source 16 is adapted to supply a low-level supply voltage V.
sub.
EE of, typically, -5.
2 volts.
The differential amplifier stage 10 and emitter-follower stage 12 are further connected in series between a signal input terminal 18 and a signal output terminal 20.
At the signal input terminal 18 is to appear a binary input signal V.
sub.
IN having a high level of, typically, -0.
75 volt and a low level of, typically, -1.
55 volt, as is also customary in the art.
The prior-art emitter-coupled logic circuit herein shown is constructed and arranged to implement a logic inverter circuit Thus, a binary output signal V.
sub.
OUT having a low level of -1.
55 volt or a high level of -0.
75 volt is to appear at the signal output terminal 20 in response to the binary input signal V.
sub.
IN of the high level of -0.
75 volt or the low level of -1.
55 volt, respectively, as will be described in more detail.
The differential amplifier stage 10 connected between the high-level and low-level supply voltage sources V.
sub.
CC and V.
sub.
EE includes transistors 22 and 24 each of the n-p-n type.
The n-p-n transistor 22 has its collector connected through a resistor 26 to the bus line leading from the high-level supply voltage source 14, while the n-p-n transistor 24 has its collector connected directly to the bus line leading from the high-level supply voltage source 14
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