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Error-correction-circuit

Parallel data transmission unit using byte error correcting code

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Error correction circuit

Details

Inventors: Kodama, Yukio; Murakami, Kazuo; Yoshida, Hideo;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Ruggiero; Joseph
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt

An error correction circuit is capable of performing correction errors in data at a high speed. A syndrome generator (2) calculates syndromes of RS codes based on partial data streams which are given from a data buffer (1). A received CRC generator (13) performs CRC coding on the partial data streams which are given from a data buffer (1) to thereby obtain received CRCs. An error pattern CRC generator (14) calculates error pattern CRCs of the respective partial data stream based on error patterns which are generated by an error pattern generation circuit (33). Under the control of a control circuit (40), the operations performed by the syndrome generator (2), the received CRC generator (13) and the error pattern CRC generator (14) are carried out at the same time. An improvement in the speed of error correction of the partial data streams performed by the error correction means directly leads to an improvement in the speed of the whole error correction.

DETAILED DESCRIPTION An error correction circuit of a first aspect of the invention comprises (a) a data buffer for storing a data stream in which a plurality of RS codes for correcting: an error in data and CRC codes for detecting an error in the data are interleaved, the data stream being formed by a first to an n-th partial data streams each processed by RS coding, the data streams including CRC data preliminary generated by CRC coding; (b) syndrome generation means for generating syndromes of RS codes in accordance with the partial data streams which have not been corrected yet; (c) first CRC coding means for performing CRC coding on the partial data streams which have not been corrected yet to thereby obtain first CRCs; (d) error correction means for calculating error locations and error values of the partial data streams in accordance with the syndromes and for correcting errors in the partial data streams in accordance with the error locations and the error values; (e) second CRC coding means for generating error patterns of the partial data streams in accordance with the error locations and the error values, coding CRCs of the error patterns and for obtaining second CRCs; (f) adding means for receiving the first or the second CRCs and calculating a total CRC which is a sum of the first or the second CRCs of the partial data streams; (g) CRC verification means for comparing the total CRC with the CRC data of the data stream and for verifying whether the means (d) has performed error correction accurately; and (h) control means for controlling the means (b) to (g) so that the first to the n-th partial data streams are serially processed and generation of a syndrome performed by the means (b) based on a j-th partial data stream (2.
ltoreq.
j.
ltoreq.
n), CRC coding on the j-th partial data stream performed by the means (c) and CRC coding on an error pattern of a (j-1)-th partial data stream performed by the means (e) are carried out simultaneously, and so that the means (g) performs verification after the means (e) has finished CRC coding on an error pattern of the n-th partial data stream

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