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Fault recovery processing for supercomputer
| Details |
Inventors: Jippo, Akira; Nakamura, Akihiko;
Assignee: NEC Corporation (Tokyo, JP)
Primary Examiner: Atkinson; Charles E.
Assistant Examiner:
Attorney, Agent or Firm: Foley & Lardner
In a high speed computer having a memory and a plurality of arithmetic processors divided into groups, the arithmetic processors of each group being connected to the memory in a hierarchical order in a master-subordinate relationship, the memory and the arithmetic processors generates an alarm signal indicating a failed part of the memory and each of the arithmetic processors. During a fault recovery process, a test program is performed on the computer to determine if it is properly functioning. If a favorable result is indicated, the computer is restarted in an original system configuration. Otherwise, part of the arithmetic processors is isolated from the computer depending on the alarm signal to degrade the computer into a first degraded system configuration. The test program is performed again on the first degraded system configuration. If the second test produces a favorable result, the computer is restarted in the first degraded system configuration. Otherwise, one or more of the arithmetic processors are isolated from the computer depending on the alarm signal so that the computer is degraded into a second degraded system configuration. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide a fault recovery method and processor for high speed computers which minimizes the system downtime.
In a high speed computer having a memory and a plurality of arithmetic processors divided into groups, the arithmetic processors of each group being connected to the memory in hierarchical order in a master-subordinate relationship, the memory and the arithmetic processors generating an alarm signal indicating a failed part of the memory and each of the arithmetic processors.
The alarm signal is analyzed to determined if the computer is in a possibly recoverable state.
If the computer is in recoverable state, a test program is performed on it to determine if it is properly functioning.
If the test program indicates that the computer is properly functioning, it is restarted in an original system configuration.
Otherwise, part of the arithmetic processors is isolated from the computer depending on the alarm signal to degrade the computer into a first degraded system configuration.
The test program is again performed on the computer in the first degraded system configuration.
If the result of the second test indicates that the computer is properly functioning, it is restarted in the first degraded system configuration.
Otherwise, one or more of the arithmetic processors are isolated from the computer depending on the alarm signal so that the computer is degraded into a second degraded system configuration to allow the computer to be restarted in the second degraded system configuration.
In a preferred form of the present invention, each of the arithmetic processors includes a plurality of vector pipelines, and a valid/invalid code is assigned to each of the arithmetic processors depending on a result of the test program, the valid/invalid code identifying each of the arithmetic processors of each group as connectable to the computer or disconnectable from the computer.
A total number of vector pipelines available for one group of the arithmetic processors is compared with a total number of vector pipelines available for the other group of the arithmetic processors
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