DETAILED DESCRIPTION FIG.
2 is a block diagram of a configurable logic block (CLB) 200 in accordance with one embodiment of the invention.
CLB 200 includes programmable interconnect resources 201, field programmable configurable logic element (CLE) circuit 202, non-field programmable sea-of-gates (SOG) gate array 203 and dedicated SOG interconnect resources 204A-204D.
CLE circuit 202 is connected to the programmable interconnect resources 201 and the SOG gate array 203.
The SOG gate array 203 is connected to the dedicated SOG interconnect resources 204A-204D.
These connections are described in more detail below.
Although the present invention is described in connection with a non-field programmable gate array which is an SOG gate array 203, it is understood that this SOG gate array 203 can be replaced with other types of non-field programmable gate arrays in other embodiments of the invention.
In general, the CLE circuit 202 and the SOG gate array 203 are made up of a plurality of active and passive circuit elements, such as transistors, diodes, capacitors and resistors, which are fabricated in a semiconductor substrate using conventional semiconductor processing methods.
Programmable interconnect resources 201 and dedicated SOG interconnect resources 204A-204D are made up of conductive traces which are formed in one or more interconnect layers over the semiconductor substrate in accordance with conventional semiconductor processing techniques.
FIG.
3 is a block diagram of a portion of an FPGA 1 which utilizes CLB 200.
The illustrated portion of FPGA 1 includes four adjacent CLBs 200, 200A, 200B and 200C, which are arranged in a grid pattern.
CLBs 200A, 200B and 200C include corresponding programmable interconnect resources 201A, 201B and 201C, CLE circuits 202A, 202B and 202C, and SOG gate arrays 203A, 203B and 203C, as illustrated.
Interconnect resources 201, 201A, 202A and 201C are shared by the adjacent CLB circuits 200, 200A, 200B and 200C as illustrated.
Similarly, the SOG interconnect resources 204A-204L are shared by SOG gate arrays in adjacent CLBs
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