Flip-flop circuit and electronic device including the flip-flop circuit

DETAILED DESCRIPTION It is an object of this invention to provide a flip-flop circuit.
The flip-flop circuit includes a dynamic circuit which is operable also in a low-frequency cycle.
A delay time, a setup time, and a hold time in the flip-flop circuit may be improved.
This permits the disadvantages described above to be eliminated.
It is another object of this invention to provide an improved computing system by using the above flip-flop circuit.
The object described above is achieved by a flip-flop circuit comprising: a master circuit including a static flip-flop with a feedback loop; and a slave circuit including a dynamic flip-flop; wherein a clock signal is applied to the master circuit and the slave circuit, a clock width of the clock signal determined by a time period from a clock edge for taking data into the master circuit to another clock edge for closing the master circuit being set to less than a given time period.
The flip-flop circuit mentioned above may further comprise a clock signal generation circuit which generates the clock signal.
In the flip-flop circuit mentioned above, the clock signal generation circuit may further generate clock signals having opposite phases which are applied to the master circuit and the slave circuit.
According to the flip-flop circuit mentioned above, a delay time in the slave circuit may be reduced.
This enables the flip-flop circuit to operate at a higher operational speed.
Further, even if a clock cycle of the clock signal becomes long, the flip-flop circuit prevents data in the slave circuit from being degraded.
The object described above is also achieved by a flip-flop circuit comprising: master flip-flops connected by a first path having a first delay; and a slave flip-flop and a master flip-flop connected by a second path having a second delay smaller than the first delay; wherein data is transmitted between the master flip-flops through the first path and is transmitted between the slave flip-flop and the master flip-flop through the second path, whereby a racing and an overdelay are prevented