Graphics system including an output buffer circuit with controlled Miller effect capacitance

DETAILED DESCRIPTION Generally, and in one form of the invention, an integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor.
The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor.
A technical advantage is that spikes which might occur due to overshoots beyond supply rail voltages are reduced or prevented while controlled switching characteristics are provided.
The buffer is applicable in any chip, circuit or system to which its advantages commend it.
Other circuits, palette devices improved with such circuits, computer graphics systems, and methods are described and claimed herein.