 Integrated circuit device having a memory and majority logic |
| I claim: 1. An integrated circuit device comprising: a memory having at least first, second and ... |
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| Logic circuit system with latch circuits for reliable scan-path testing |
| It is, therefore, a primary object of the present invention to provide an IC logic circuit having ... |
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| Optional single or double clocked latch |
| The present invention is especially directed towards a programmable latching circuit which can ... |
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| Dynamic logic circuit with reduced operating current |
| Accordingly, it is an object of the present invention to provide a dynamic logic circuit which has ... |
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| Edge sensitive set-reset flip flop |
| Accordingly, it is the object of this invention to provide an improved edge sensitive set-reset ... |
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| Master-slave multivibrator with improved metastable response characteristic |
| In accordance with the present invention, a master-slave flip-flop device having a master segment ... |
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| Arbiter circuits with metastable free outputs |
| The two-input arbiter circuit shown in FIG. 1 includes input terminals 10 and 11 and output ... |
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| One or more input asynchronous register |
| The present invention is directed to a unique register configured like an edge-triggered "D" type ... |
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| Fast sense amplifier |
| With reference to FIG. 1 there is shown a sense amplifier 10. An NPN transistor 11 has a base 17 ... |
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High density programmable logic device
| Details |
Inventors: Agrawal, Om P.; Landers, George H.; Schmitz, Nicholas A.; Moench, Jerry D.; Ilgenstein, Kerry A.;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Santamauro; Jon
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill, MacPherson, Franklin & Friel, LLP, Gunnison; Forrest E.
Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs. |
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DETAILED DESCRIPTION The programmable logic device (PLD) of this invention is a high density segmented PAL-like device which gives an optimum balance between functionality, silicon die size, and performance.
The high density programmable logic device has two or more programmable logic circuits (blocks) interconnected by a switch matrix.
In one embodiment, four programmable logic blocks contained in a single integrated circuit are interconnected by a switch matrix while in another embodiment two programmable logic blocks are interconnected by a switch matrix.
This segmented logic structure provides high speed performance while maintaining greater functionality than was available in prior art programmable logic devices.
The switch matrix has a bank of programmable multiplexers for each programmable logic block in the PLD.
The input signals to the multiplexers in each bank are selected from input signals on the pins of the integrated circuit package containing the integrated circuit of this invention and output signals from the programmable logic blocks.
Hence, the switch matrix functions as both an input means and a feedback means to the various logic circuits.
Each of the multiplexers in the switch matrix has configuration architecture cells which provide input select signals to the multiplexer.
The input select signals configure the multiplexer so that one of the signals on an input line to the multiplexer is passed through the multiplexer to an output line of the multiplexer and the other signals on the remaining input lines are disconnected from the output line.
The programmable logic blocks of this invention communicate with each other only through the switch matrix.
Moreover, the programmable logic blocks receive all input signals from the switch matrix.
Thus, the programmable logic blocks may be viewed as independent programmable logic devices on the same integrated circuit chip.
In one embodiment, each programmable logic block of this invention includes a programmable logic array, a programmable logic allocator, programmable logic macrocells, and programmable I/O macrocells
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CPUs 
