High performance single port RAM generator architecture

DETAILED DESCRIPTION According to the present invention, a single-port RAM generator, in a CAD environment, generates different RAM structures.
The generated RAM structure has a static RAM (SRAM) matrix and a self-timed control architecture.
The SRAM matrix has at least one row which corresponds to a word line and at least one column which corresponds to a bit line.
The self-timed control architecture has a dummy row which has an equivalent load of a word line in the SRAM matrix and corresponds to a row in the SRAM matrix; and a dummy column which has the equivalent load of a bit line in the SRAM matrix and corresponds to a column in the SRAM matrix.
Discharge cells are in the input portion of the dummy column and they enable the dummy column to be discharged at a faster rate than the corresponding bit column in the SRAM matrix.
Preferably, the structure of the basic SRAM cells of the SRAM matrix is a couple of small inverters latches connected back to back with corresponding pass transistors connected to the bit line of the SRAM matrix.
The structure of the discharge cells is a couple of transistors, of the MOS type, both connected between the dummy column and ground.
The drain of the first transistor is connected to the dummy column and the source of the first transistor is connected to the drain of the second transistor.
The source of the second transistor is connected to ground and the gate of the first transistor connected to the supply voltage.
All gate terminals of first transistors are connected together and receive a same dummy row selection signal.
The structural and functional features of SRAM matrix and the self-timed control architecture allows variations in parameters introduced by the user in a CAD environment.
In a preferred embodiment of the RAM structure for RAM operations, a control logic, with control logic inputs of a clock signal and a write enable signal, is an additional element of the self-timed control architecture.
The control logic has a duty cycle independent read cycle activated by the falling edge of the clock signal, with the output of the controllogic having an output connected to the dummy row