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 High speed parallel binary multiplier

Details
Inventors: Kronlage, John W.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Harkcom; Gary V.
Assistant Examiner: Mai; Tan V.
Attorney, Agent or Firm: Fitzgerald; Thomas R., Heiting; Leo N., Sharp; Melvin

An n.times.n bit multiplier of a type having input and output registers and associated multiplexers, a multiplier array and adders, a shifter and an accumulator. The multiplier includes a temporary register having an input coupled in parallel with an input of the accumulator to an output of the shifter and an output coupled to a multiplexer for controlling the flow of output data from the temporary register to the multiplier array. The temporary register is responsive to a SELREG control signal to become enabled and disabled. An input of the shifter is coupled to an output of the adder.

DETAILED DESCRIPTION According to the invention there is provided a multiplier circuit which employs a temporary register whose input is coupled in parallel with the input of the accumulator to a shifter.
Clock signals applied to the temporary register and accumulator determine whether the shifter output is stored in the temporary register or in the accumulator.
The temporary register can be used to store temporary data, constants and scaled binary fractions.


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