 Logic circuit |
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| Control module for reducing ringing in digital signals on a transmission line |
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| For conditioning the input to or the output from an integrated circuit |
| The present invention has been developed to obviate the above-described problems and has as its ... |
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| Apparatus for sensing data in data bus lines |
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| Programmable circuit arrangement |
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| Read-only memory with few programming signal lines |
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| System for dynamically exchanging and matching revision information between host and terminal |
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| Registered logic macrocell with product term allocation and adjacent product term stealing |
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| Apparatus and method for product term allocation in programmable logic |
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| Level converter circuit for converting ECL-level input signals |
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High speed state machine
| Details |
Inventors: Pumo, Joseph; Atwell, Jr., William D.; McAlister, Doyle V.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Wambach; M. R.
Attorney, Agent or Firm: Fisher; John A., Van Myers; Jeffrey
A state machine in which the next state signals are biased by the next state encoder very close to the switch voltage of the input transistors of the present state latches to improve the response time of the state machine. Charge sharing on the outputs of the next state selector is prevented from affecting the biased next state signals by voltage substaining circuitry. By pre-encoding input signals pertinent to each state using separate input logic, the size of the next state selector is minimized, further improving the response time of the state machine. Selected present state latches may be prevented from changing state by gating the next state signals. |
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DETAILED DESCRIPTION Accordingly, it is an object of the present invention to provide a state machine in which the inputs to the present state latches are biased to increase speed of transistion.
Another object of the present invention is to provide a state machine having a next state selector and a next state encoder which are highly optimized in order to increase the response time thereof.
In carrying out these and other objects of the present invention, there is provided, in one form, a state machine comprising a present state latch, a present state decoder, a next state selector and a next state encoder.
The present state latch, which is responsive to the voltage of a next state signal relative to a predetermined switch voltage, stores the state of the next state signal in response to a first clock signal.
Thereafter, the present state latch provides a present state signal in response to a second clock signal, the present state signal having a state related to the state of the stored next state signal.
The present state decoder, which is responsive to the state of the present state signal provided by the present state latch, provides a present state control signal in response to the first clock signal, the present state control signal having a state related to the state of the present state signal.
The next state selector, which is responsive to the state of the present state control signal provided by the present state decoder and at least a first input signal generated externally to the state machine, provides a next state select signal in response to the first clock signal, the next state select signal having a state related to a predetermined logical combination of the states of the present state control signal and the first input signal.
Thereafter, the next state selector forces the next state select signal to a predetermined state in response to the second clock signal.
The next state encoder, which is responsive to the state of the next state select signal provided by the next state selector, provides the next state signal to the present state latch in response to the first clock signal, the next state signal having a state related to the state of the next state select signal
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CPUs 
