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 Insulated gate field-effect transistor read-only memory array

Details
Inventors: Bell, Antony G.;
Assignee: Fairchild Camera and Instrument Corporation (Mountain View, CA)
Primary Examiner: Fears; Terrell W.
Assistant Examiner:
Attorney, Agent or Firm: MacPherson; Alan H., Colwell; Robert C.

An array of read-only memory cells is formed from a plurality of insulated gate field-effect transistors. Information may be programmed into individual transistors within the array by application of selected potentials to the connecting lines of the array. An individual cell is programmed by causing some of the electrons flowing between the source and drain to acquire sufficient energy to be injected into and trapped in the insulating material separating the channel from the gate electrode. The trapped electrons cause a change in the current-voltage characteristics of the transistor, which may be detected during reading of the memory cell most easily by reversing the polarity of the source and the drain. Embodiments of such an array are shown and may be utilized as a ROM, PROM and EPROM.

DETAILED DESCRIPTION Applicant has discovered that the phenomenon of hot electron trapping may be utilized to fabricate improved arrays of IGFET memory cells.
One cell of such an array may be fabricated with well known MOS technology and may be programmed electrically by applying suitable potentials to its source, drain and gate electrodes.
By biasing the IGFET into its pinch-off region, hot electrons are generated which are injected, rather than tunneled, from the channel into the gate insulating material where they are trapped.
The trapped electrons cause a shift in the current-voltage characteristics of the IGFET which is greatest if the IGFET is programmed in one mode and operated in the opposite mode, that is, with the source and drain terminals reversed.
The change in current-voltage characteristics of individual cells can be representative of information.
One cell of applicant's array may be fabricated simply according to well known MOS fabrication processes.
Because the memory cell is simple in design, it occupies a relatively small amount of wafer surface area, following large dense arrays.
Also, unlike prior-art MNOS- and FAMOS-type devices, no particularly thin regions of insulating material are required.
This allows higher yields, lower cost and greater reliability.
Applicant has discovered that the memory cells may be arranged in a variety of arrays to create ROM's, PROM's and EPROM's.
In one embodiment of the invention, a plurality of IGFET's each have a source connected to a single common line, a gate connected to one of a plurality of x lines and a drain connected to one of a plurality of y lines.
By application of appropriate signals to the common line and the x and y lines, information may be stored in any desired IGFET and later retrieved.
In another embodiment, a plurality of IGFET's each have a gate connected to one of a plurality of i lines, a source connected to one of a plurality of j lines and a drain connected to one of a plurality of k lines.
By application of suitable signals to the i, j and k lines, information may be stored in and later retrieved from any desired cell



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