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Integral transform method
| Details |
Inventors: Baldwin, David R.;
Assignee: Du Pont Pixel Systems Limited (Stevenage, GB)
Primary Examiner: Shaw; Dale M.
Assistant Examiner: Mai; Tan V.
Attorney, Agent or Firm: Worsham, Forsythe, Sampels & Wooldridge
A method of performing an integral transform operation (such as a Fast Fourier Transform), wherein the underlying algorithm is partitioned to provide an efficient sequence of data operations. Preferably the address calculations are performed separately from the data calculations, and the algorithm is partitioned so that the microcode sequence for all but the last few data calculations is constant. Thus, the bandwidth at the interface to the numeric processor is conserved, and control storage in the numeric processor is also efficiently conserved. Moreover, the preferred partition for performing Fast Fourier Transform manipulates data in reasonably large subsets (e.g. 8 floating-point words at a time). This turns out to use less data bandwidth than would be required using smaller data subsets. |
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DETAILED DESCRIPTION What is claimed is: 1.
A method of performing an integral transform operation, comprising the steps of: loading a data set, corresponding to values on which the integral transform is desired to be performed, into a data cache; repeatedly performing address calculations on a first processor, to determine which subset of said data set should next be operated on, and controlling data transfers between said data cache and a second processor accordingly; repeatedly performing data calculations in said second processor, on respective subsets as transferred by said first processor, wherein said second processor runs asynchronously to and concurrently with said first processor; wherein said address calculations, said data transfers, and said data calculations correspond to a partition of said integral transform into a number of butterfly operation stages which is at least equal to the logarithm, to the base two, of the number of data points to be transformed; and wherein, at each of said butterfly operation stages except for a small fixed number thereof, said second processor executes the same sequence of program operations.
2.
The method of claim 1, wherein said second processor reads at least 256 bits of data on substantially every read access to said data cache.
3.
The method of claim 1, wherein each said subset includes eight words of said data set, and said second processor executes the same sequence of program operations during all of said butterfly operations except for two thereof.
4.
The method of claim 1, wherein said integral transform operation is a discrete Fourier transform.
5.
The method of claim 1, wherein each said data set includes 1024 data points, and said second processor executes the same sequence of program operations during eight of said butterfly operations.
6.
The method of claim 1, wherein said second processor is connected to a data cache by a bus with at least 8 times as many data lines as the number of bits of precision used in calculations within said second processor
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CPUs 
