Integrated sample and hold circuit

DETAILED DESCRIPTION The present invention overcomes this inherent inapplicability of bipolar semiconductor devices by providing a high speed sample and hold circuit comprising bipolar semiconductor and associated devices which may be made using integrated circuit techniques.
In the preferred embodiment of the invention, such a circuit is provided composed only of NPN transistors as active components, plus resistors and capacitors.
This is made possible by a sample and hold circuit comprising a first bipolar transistor means having a base coupled to receive an input signal.
A capacitor is coupled to the transistor for storing a voltage representative of the input signal while the transistor is turned on, and for storing a voltage representative of the input signal at the time the transistor is turned off while the transistor is turned off.
Means is also provided for biasing selectively the transistor appropriately for turning it on and off.
Means is also preferably provided for applying selectively relatively higher and lower voltages on the capacitor.
Means for controlling the transistor biasing and the capacitor voltage is provided such that when the transistor is biased to turn off, the relatively higher voltage is applied to the capacitor.
The capacitor then carries a voltage representative of the input signal existing when the transistor is turned off plus the higher voltage.
This assures that the transistor will not turn back on while the circuit is in the hold state.
In the preferred embodiment of a sample and hold circuit made according to the present invention, a pair of input terminals receives a differential input signal.
A pair of output terminals transmit a differential output signal.
A control signal generator generates a pair of complementary control signals having a first state during which the voltage of the input signal existing when the control signal assumes the first state is held on the output terminals.
A first and second capacitor are coupled together and to the output terminals for storing respective complementary voltages on the output terminals