Latched fedback memory finite-state-engine

DETAILED DESCRIPTION The present invention has been contemplated to overcome the foregoing deficiencies and meet the above described needs.
The latched fedback-memory finite-state-engine of the present invention does not require synchronization circuitry for its own internal operations because it utilizes latches to isolate or "freeze" a stable input and thus produce a stable output.
Further, the operation of the finite-state-engine is totally, inherently synchronized by an outside supplied clock signal which can be altered upon demand.
The finite-state engine comprises three latches, such as parallel-entry shift registers, and a function module, such as a memory device, used to store the finite-state equations.
The operation of the finite-state engine is controlled by the receipt of an outside supplied clock signal to the latches.
A first latch has an input data set X and produces a stable output X.
sub.
1, which is an isolated subsection of X, upon the receipt of the clock signal.
The function module stores the finite state equations and has as an input X.
sub.
1 and Y.
sub.
1, and has an output Y.
sub.
1 ' and Y.
sub.
2 '.
A second latch has as an input Y.
sub.
1 ' and produces an output Y.
sub.
1 upon the receipt of the same clock signal.
A third latch has as an input Y.
sub.
2 ' and produces an output Y.
sub.
2 upon the receipt of a following clock signal.