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Logic gates with controllable time delay
These needs are met by providing a variable threshold voltage logic element. The threshold voltage is controllably varied, using multiplication means, summation means ...
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Programmable logic cell and array
OF DRAWING FIG. 1 depicts an array 10 of cells 20 formed in accordance with the present invention. As is apparent, the cells are arranged in a two dimensional matrix ...
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Output logic macrocell with enhanced functional capabilities
This invention provides an output logic macrocell for use with a logic block such as a programmable logic array. The output logic macrocell contains an XOR gate, an OR ...
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Graphics system including an output buffer circuit with controlled Miller effect capacitance
Generally, and in one form of the invention, an integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage ...
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Safestore frame implementation in a central processor
What is claimed is: 1. In a central processor including: A) data manipulation means for performing successive data manipulation operations and for making safestore ...
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Refresh control for dynamic memory in multiple processor system
In accordance with one embodiment of the invention, a computer system employs three identical CPUs typically executing the same instruction stream, and has two identical,...
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System and method for providing a fault tolerant computer program runtime support environment
The present invention automatically converts a non-fault tolerant software program into a fault-tolerant software program. To achieve this goal, the invention includes ...
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Multiple processor synchronized halt test arrangement
An object of this invention is to provide a stable testing and debugging environment for a multiprocessor system and the ability to examine one or all processors when ...
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High-availability computer system with a support logic for a warm start
It is an object of this invention to control the assignment of the logic processors to operating status in such a manner that in the course of several start phases, i.e.,...
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Redundant read bus for correcting defective columns in a cache memory
Generally, the present invention relates to efficiently implementing column redundancy in a cache memory architecture to reach high speed performance. The invention ...
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