Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home CPUs Logic-gates-with-controllable-time-delay

 Fault diagnostic distributed processing method and system
It is an object of the present invention to provide a distributed processing system which resolves ...


 Method and system for identification of software application faults
What is claimed is: 1. A method for identification of a fault in a software application associated ...


 System for reading system log
The inventive remote access system provides system administrators with new levels of client/server ...


 Shift register programming for a programmable logic device
The present invention describes a novel architecture to improve the performance of a programmable ...


 Complementary logic input parallel (CLIP) logic circuit family
It is therefore an object of the present invention to provide a high speed complementary all-...


 Router device and data communication system capable of suppressing traffic increase in communications among a plurality of lan segments
An object of the present invention is to provide a router device and a data communication system ...


 Bus adapter module with improved error recovery in a multibus computer system
It is an object of the present invention to provide a method and apparatus for error recovery in a ...


 Error correction circuit
An error correction circuit of a first aspect of the invention comprises (a) a data buffer for ...


 Virtual machine data processor
Accordingly, it is an object of the present invention to provide a data processor which can support ...


 Distributed processing system with checkpoint restart facilities wherein checkpoint data is updated only if all processors were able to collect new checkpoint data
It is therefore an object of the present invention to provide a distributed processing system with ...


 Logic gates with controllable time delay

Details
Inventors: Corcoran, John J.; Poulton, Kenneth D.;
Assignee: Hewlett-Packard Company (Palo Alto, CA)
Primary Examiner: Westin; Edward P.
Assistant Examiner: Sanders; Andrew
Attorney, Agent or Firm:

Apparatus for introduction of a controllable time delay in the transition of a logic device output signal from a first logical level to a second logical level, in response to change of an input signal, or the difference of two input signals from a third logical level to a fourth logical level, delivered to the logic device. In a first embodiment, a limiting amplifier receives an input signal S.sub.in and a threshold signal V.sub.T at its two terminals and forms an amplified difference output signal S.sub.out. A selected voltage level signal V.sub.L and S.sub.out are received at a signum function module and the output signal sgn(S.sub.out -V.sub.L) is formed and issued. The signum output signal is multiplied by a controllable real number m and is added to V.sub.L to form the threshold signal V.sub.T. The desired output signal S.sub.out makes a transition between the first and second logical levels, with a time delay that is controllable by choice of the number m. In a second embodiment, which also uses a signum function, two input signals, S.sub.in,1 and S.sub.in,2, give rise to two output signals, S.sub.out,1 and S.sub.out,2, and the difference signal S.sub.out,1 -S.sub.out,2 makes a transition between two logical levels with a time delay that depends controllably on choice of the number m.

DETAILED DESCRIPTION These needs are met by providing a variable threshold voltage logic element.
The threshold voltage is controllably varied, using multiplication means, summation means and Signum function means.
In one embodiment where a single signal controls the change of logical level, a limiting amplifier provides one of two input signals for a Signum function module (sgn(x) = x/abs(x) for x .
noteq.
0, where abs(x) is the absolute value of the number x), with the other input signal being determined by a threshold voltage V.
sub.
L.
Multiplication means is also provided, having two input terminals and an output terminal, for receiving the output signal of the Signum function module at a first input terminal, for receiving a first control input signal representing a numerical value m at a second input terminal, and for forming and issuing the product of these two input signals at the output terminal.
This apparatus includes summation means, having two input terminals and having an output terminal that is connected to the positive (or negative) input terminal of the amplifier, for receiving the multiplication means output signal at a first input terminal, for receiving a second control signal representing a logic threshold value V.
sub.
L at a second input terminal, and for forming and issuing at the output terminal the sum V.
sub.
T of these two input signals.
If an input signal S.
sub.
in is received at the negative input terminal of the amplifier and crosses the threshold level V.
sub.
T at a time t = t.
sub.
O, the output signal issued by the limiting amplifier undergoes a change from one logical level to another logical level at a time t = t.
sub.
O + t.
sub.
d + .
DELTA.
t.
sub.
d, where .
DELTA.
t.
sub.
d is a controllable time delay interval that depends upon m and t.
sub.
d is the time delay of the amplifier for m=0.
A second embodiment for introducing a controllable time delay uses the difference of two independent input signals.
The apparatus includes signal input means having one or more input terminals and two output terminals, for receiving input signals S



Related patents
  Programmable logic cell and array
OF DRAWING FIG. 1 depicts an array 10 of cells 20 formed in accordance with the present invention. As is apparent, the cells are arranged in a two dimensional matrix ...
  Output logic macrocell with enhanced functional capabilities
This invention provides an output logic macrocell for use with a logic block such as a programmable logic array. The output logic macrocell contains an XOR gate, an OR ...
  Graphics system including an output buffer circuit with controlled Miller effect capacitance
Generally, and in one form of the invention, an integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage ...
  Safestore frame implementation in a central processor
What is claimed is: 1. In a central processor including: A) data manipulation means for performing successive data manipulation operations and for making safestore ...
  Refresh control for dynamic memory in multiple processor system
In accordance with one embodiment of the invention, a computer system employs three identical CPUs typically executing the same instruction stream, and has two identical,...
  System and method for providing a fault tolerant computer program runtime support environment
The present invention automatically converts a non-fault tolerant software program into a fault-tolerant software program. To achieve this goal, the invention includes ...
  Multiple processor synchronized halt test arrangement
An object of this invention is to provide a stable testing and debugging environment for a multiprocessor system and the ability to examine one or all processors when ...
  High-availability computer system with a support logic for a warm start
It is an object of this invention to control the assignment of the logic processors to operating status in such a manner that in the course of several start phases, i.e.,...
  Redundant read bus for correcting defective columns in a cache memory
Generally, the present invention relates to efficiently implementing column redundancy in a cache memory architecture to reach high speed performance. The invention ...
  Plural sensor monitoring and display device
We claim: 1. In a monitoring device for monitoring the outputs of a plurality of sensors and displaying appropriate information, said device comprising: a plurality of ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved