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| Programming architecture for a programmable integrated circuit employing antifuses |
| OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing how FIGS. 1A, 1Ba, 1Bb, 1Bc, 1C, 1D, 1E, 1... |
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| High density programmable logic device |
| The programmable logic device (PLD) of this invention is a high density segmented PAL-like device ... |
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| Dedicated local line interconnect layout |
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| Tile-based modular routing resources for high density programmable logic device |
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| Programmable logic array integrated circuits |
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| Electric socket adapter |
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| Memory arbitration between timekeeping circuitry and general purpose computer |
| It is, therefore, an object of this invention to provide a method and circuitry for arbitrating ... |
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Logic level control for current switch emitter follower logic
| Details |
Inventors: Ashton, Gerard J.; Cavaliere, Joseph R.; Cheng, Ming T.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Bertelson; David R.
Attorney, Agent or Firm: Ellis; William T.
A logic circuit network with circuitry for independently controlling at least one of the logic levels generated thereby, comprising, in one embodiment, a logic circuit with an output current node, a complement output current node, and at least one input line, the circuit for generating an output voltage level at the output current node which depends on the amount of current drawn therethrough, and for generating a complement output voltage level at the complement output current node which depends on the amount of current drawn therethrough; in combination with a current drawing means for drawing a controlled amount of current through one of those nodes to adjust the voltage level at that node. In one embodiment, this current drawing means is connected to a voltage reference level V.sub.R1, and operates to draw an amount of current from whichever current node is at a voltage level which is closest to a predetermined constant plus this voltage reference level V.sub.R1. The amount of current drawn is controlled to cause this closest node voltage level to approach this predetermined constant plus V.sub.R1. In a preferred embodiment this current drawing means comprises a separate differential amplifier connected to each of the output current nodes. |
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DETAILED DESCRIPTION Briefly, the present invention comprises a logic circuit network for producing both a first logic level and a different adjustable second logic level in response to at least one input signal, comprising: a logic circuit with an output current node, a complement output current node, and at least one input line, with the logic circuit for generating an output voltage level at the output current node which depends on the amount of current drawn through the output current node, and for generating a complement output voltage level at the complement output current node which depends on the amount of current drawn through the complement output current node; and means connected to a voltage reference level V.
sub.
R1, with this means for drawing an amount of current from whichever of the output current node or the complement current node has a voltage level V which is closest to a predetermined constant plus the voltage reference V.
sub.
R1, and wherein the amount of current drawn by the current drawing means is sufficient to cause the closest voltage level V to approach the predetermined constant plus the voltage reference level V.
sub.
R1.
In a preferred embodiment of the present invention, the current drawing means comprises a first differential amplifier circuit connected to the output current node and having a reference side thereof connected to the voltage reference level V.
sub.
R1 ; and a second differential amplifier circuit connected to the complement output current node and having a reference side thereof connected to the voltage reference level V.
sub.
R1.
In yet a further embodiment of the present invention, this current drawing means may comprise a first voltage level shifting circuit for shifting the output voltage level at the output current node; wherein the first differential amplifier circuit includes an input side for drawing current from the output current node; a second voltage level shifting circuit for shifting the complement output voltage level at the complement output current node; and wherein the second differential amplifier circuit includes an input side for drawing current from the complement output current node
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CPUs 
