 Memory arbitration between timekeeping circuitry and general purpose computer |
| It is, therefore, an object of this invention to provide a method and circuitry for arbitrating ... |
|
| Transition for electrical apparatus |
| I claim: 1. An electrical transition comprising: a) a nonconductive base having extending upwardly ... |
|
| Microprogram control system |
| The present invention intends to eliminate the above disadvantages and has for its object to ... |
|
| Data bank priority system |
| OF THE PREFERRED EMBODIMENT Turning now to the drawings, there is shown in FIG. 1 part of a data ... |
|
| Integrated circuit device having a memory and majority logic |
| I claim: 1. An integrated circuit device comprising: a memory having at least first, second and ... |
|
| Logic circuit system with latch circuits for reliable scan-path testing |
| It is, therefore, a primary object of the present invention to provide an IC logic circuit having ... |
|
| Optional single or double clocked latch |
| The present invention is especially directed towards a programmable latching circuit which can ... |
|
| Dynamic logic circuit with reduced operating current |
| Accordingly, it is an object of the present invention to provide a dynamic logic circuit which has ... |
|
|
Method and apparatus for calculating an error detecting code block in a disk drive controller
| Details |
Inventors: Wilson, Carrel;
Assignee: EMC Corporation (Hopkinton, MA)
Primary Examiner: Chung; Phung M.
Assistant Examiner:
Attorney, Agent or Firm: Caracappa; David N.
A disk drive controller includes a memory for storing a plurality of blocks each having a predetermined size, and a parity engine. The parity engine includes a data buffer RAM for storing a block having the predetermined size. A function circuit has a first input terminal coupled to the disk drive controller memory, a second input terminal coupled to the output of the data buffer RAM, and an output terminal coupled to the input of the data buffer RAM. A command circuit, conditions the function circuit and the data buffer RAM to operate in a first operating mode to retrieve a block from the disk drive controller memory and store it in the data buffer RAM, and in a second operating mode to calculate the exclusive-OR (XOR) of a block from the disk drive controller memory with a block from the data buffer RAM and store the result in the data buffer RAM. |
|
DETAILED DESCRIPTION OF THE DRAWINGS FIG.
1 is a block diagram of a computer system including a disk drive subsystem according to the present invention.
In FIG.
1, a plurality of N central processing units (CPUs) 10 are a plurality of M disk drive units 30 through a disk drive controller 20.
Each of the respective CPUs 10: CPU 1 12, CPU 2 14 and CPU N 19 are coupled to the disk drive controller 20 through a corresponding bi-directional channel.
In the illustrated embodiment, for example, each of the CPUs 12, 14 and 19 are coupled to the disk drive controller 20 via known SCSI bus channels.
Each of the respective disk drives 30: DISK 1 32, DISK 2 34 and DISK M 39 are also coupled to the disk drive controller 20 through corresponding bi-directional channels.
In the illustrated embodiment, for example, each of the disk drives 32, 34 and 39 are also coupled to the disk drive controller 20 via known SCSI bus channels.
In operation, the disk drive controller 20 operates to provide RAID 5 storage to the plurality of CPUs 10, utilizing the plurality of disk drives 30 as its disk drive array.
In a write operation, one of the plurality of CPUs sends a write request accompanied by data to be written to a specified location on the disk drives to the disk drive controller 20 via its SCSI bus channel.
The disk drive controller 20 partitions the write data from the CPU into appropriate sized blocks.
The disk drive controller 20 then calculates appropriate error detecting code blocks corresponding to the partitioned data blocks, in a manner known in RAID 5 disk drive systems.
When the error detecting code blocks have been calculated, the disk drive controller 20 stores the data blocks and the corresponding error detecting code blocks into the appropriate locations on appropriate disk drives among the plurality of disk drives 30 via the appropriate SCSI bus channels.
In a read operation, one of the CPUs 10 sends a read request to the disk drive controller 20 via its SCSI bus channel specifying the location on the disk drives 30 containing the desired data
|
| Related patents |
|
|
Semiconductor junction antifuse circuit
A junction antifuse is formed by one or more reverse-biased semiconductor junctions. In one embodiment of the invention, two n+ regions are spaced apart in a p-type ...
|
|
|
Programmable logic array intergrated circuit devices
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit ...
|
|
|
Scalable multiple level tab oriented interconnect architecture
An improved field programmable gate array (FPGA) is provided which includes tab network connectors for interfacing groups of logic cells with lower levels of ...
|
|
|
Programming architecture for a programmable integrated circuit employing antifuses
OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing how FIGS. 1A, 1Ba, 1Bb, 1Bc, 1C, 1D, 1E, 1Fa, 1Fb, 1Fc, 1G, 1H, 1I, 1Ja, 1Jb, 1Jc, 1K, 1L, 1M, 1Na, 1Nb, 1Nc, 10...
|
|
|
High density programmable logic device
The programmable logic device (PLD) of this invention is a high density segmented PAL-like device which gives an optimum balance between functionality, silicon die size, ...
|
|
|
Dedicated local line interconnect layout
An electrical connection arrangement for a programmable integrated circuit is described. An electrical device is disposed proximate to a vertical arranged longline which ...
|
|
|
Tile-based modular routing resources for high density programmable logic device
The present invention relates to signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a ...
|
|
|
Programmable logic array integrated circuits
The present invention provides programmable logic array integrated circuits in which signal conductors are interconnected not by relatively large and complex ...
|
|
|
One chip microcomputer having programmable I/O terminals programmed according to data stored in nonvolatile memory
A one-chip microcomputer according to the present invention is characterized by an initial reset circuit for producing a first initial reset signal having a first reset ...
|
|
|
Electric socket adapter
In accordance with this invention, a socket adapter having any combination of a rectifier, bilateral SCR or thermistor housing therein is provided for advantageous use ...
|
|
|
CPUs 
