 Method of automatically extracting a contrasting object in a digital image |
| What is claimed is: 1. A method for extracting a contrasting object in a digital image comprising: ... |
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| Computer memory apparatus |
| The above and other objects are achieved in a preferred embodiment of the memory subsystem of the ... |
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| Electro-optic binary adder |
| What is claimed is: 1. An electro-optic adder for summing binary addends having N bits comprising: ... |
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| Resolution conversion of bitmap images using error term averaging |
| OF AN ILLUSTRATIVE EMBODIMENT In FIG. 1, an image conversion system is shown having an image ... |
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| Method for testing a transceiver, and base station of a time-divisional radicommunication system |
| FIG. 1 shows part of a preferred embodiment of the base station according to the invention. FIG. 1 ... |
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| N+K sparing in a telecommunications switching environment |
| FIGS. 1 and 2 show in block diagram form an illustrative switching system of a self-routing ... |
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| Heatsink package for flip-chip IC |
| Accordingly, it is a general object of the present invention to provide a novel and useful ... |
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Method and apparatus for encoding/decoding image data
| Details |
Inventors: Normile, James O.; Yeh, Chia L.; Wright, Daniel W.; Chu, Ke-Chiang;
Assignee: Apple Computer, Inc. (Cupertino, CA)
Primary Examiner: Couso; Yon J.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
An apparatus and method for processing video data for compression/decompression in real-time. The apparatus comprises a plurality of compute modules, in a preferred embodiment, for a total of four compute modules coupled in parallel. Each of the compute modules has a processor, dual port memory, scratch-pad memory, and an arbitration mechanism. A first bus couples the compute modules and a host processor. Lastly, the device comprises a shared memory which is coupled to the host processor and to the compute modules with a second bus. The method handles assigning portions of the image for each of the processors to operate upon. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention relates to a method and apparatus for video encoding/decoding.
In the following description, for the purposes of explanation, specific values, signals, coding formats, circuitry, and input formats are set forth in order to provide a thorough understanding of the present invention.
It will be apparent, however, to one skilled in the art, the present invention may be practiced without these specific details.
In other instances, well known circuits and devices are shown in block diagram form in order to not unnecessarily obscure the present invention.
A portion of the disclosure of this patent document contains material which is subject to copyright protection.
The copyright owner has no objection to the facsimile reproduction by any one of the patent disclosure, as it appears in the Patent and Trademark Office patent files of records, but otherwise reserves all copyright rights whatsoever.
Referring to FIG.
4, an architecture of a parallel processing system which is used for compression/decompression of moving video images in the preferred embodiment is shown as 400.
The architecture of the preferred embodiment provides a parallel coupling of multiple video processing modules such as 401-404 which has the necessary bandwidth to decompress video images at the frame rates required by motion video (for instance, 30 frames per second).
Modules 401-404 are coupled to a computer system bus 425 via control bus 412 in the preferred embodiment.
Also, coupled to system bus 425 is display controller 426, which is coupled to frame buffer 427.
Frame buffer 427 in turn is coupled to display 426 for displaying information.
In the preferred embodiment, information is placed onto bus 425 by modules 401-404 or host processor 410, and read in by display controller 426 for placing into frame buffer 427 and display on 428.
Although host processor 410, in the preferred embodiment, is typically the bus master of system bus 425, at certain times display controller 426 assumes control of system bus 425
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