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| Apparatus and methods for modulation and demodulation of data |
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| Insulated gate field-effect transistor read-only memory array |
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| Non-volatile semiconductor memory device |
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Method and apparatus for manufacturing known good semiconductor die
| Details |
Inventors: Farnworth, Warren; Wood, Alan;
Assignee: Micron Technology, Inc. (Boise, ID)
Primary Examiner: Arbes; Carl J.
Assistant Examiner:
Attorney, Agent or Firm: Gratton; Stephen A.
A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed. |
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DETAILED DESCRIPTION In accordance with the present invention, a method and apparatus for manufacturing known good die are provided.
The method of the invention, generally stated, includes the steps of: fabricating a semiconductor wafer containing a plurality of dice; testing the gross functionality of the dice and mapping the wafer; sawing the wafer into discrete die; assembling each discrete die in a carrier having an interconnect and a force distribution mechanism adapted to bias the die and interconnect together; testing the die using the carrier and recording the test data; disassembling the carrier to remove the tested die; and then continuing processing of the tested die for shipment.
The carrier is adapted to retain the die under test and provide a temporary electrical connection between the die and external test circuitry.
This enables burn-in and other test procedures to be performed on the die.
The carrier includes a carrier base with external connectors and an interconnect for establishing temporary electrical communication between the die and the external connectors.
In addition to the base and temporary interconnect, the carrier includes a force distribution mechanism for retaining and biasing the die and the interconnect together.
The force distribution mechanism includes a bridge clamp, a spring clip and a pressure plate.
The carrier base, interconnect and force distribution mechanism are designed for efficient assembly and disassembly of the carrier with a die.
The temporary interconnect is formed in a configuration which accommodates a particular die bondpad configuration (e.
g.
, peripheral, array, edge connect, end connect, lead over chip (LOC)) and bondpad structure (e.
g.
, flat pad, solder ball, bumped pad).
Different types of interconnects are thus interchangeable to allow testing of the different types of semiconductor dice using a universal carrier.
The interconnect includes raised contact members for contacting contact locations (e.
g.
, bond pads, test pads) on the die to form an electrical connection
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