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Home CPUs Method-for-storing-data-from-an-external-processor-in-storage-devices-through-buffer-devices

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 Method for storing data from an external processor in storage devices through buffer devices

Details
Inventors: Nguyen, Anh; Gajjar, Kumar;
Assignee: MTI Technology Corporation (Anaheim, CA)
Primary Examiner: Dixon; Joseph L.
Assistant Examiner: Nguyen; Hiep T.
Attorney, Agent or Firm: Townsend and Townsend Khourie and Crew

A data storage system having a local processor and a plurality of memory storage elements is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers, each coupled to a separate memory storage element. A data path control circuit is programmed by the local processor to control the transfer of data between the external CPUs and the memory buffers. Two interface circuits are coupled between the external CPUs and the memory buffers to provide two data paths for transferring data between the external CPUs and the memory buffers. The data path control circuit contains two independent sequencing circuits for selecting memory buffers. This allows one data path to be used for reading or writing to a number of the memory buffers while the other data path is simultaneously used for a different operation for the rest of the memory buffers.

DETAILED DESCRIPTION According to the invention, a data storage system having a local processor and a plurality of memory storage elements is used for storing data from one or more external CPUs.
The storage system includes a plurality of memory buffers, each coupled to a separate memory storage element.
A data path control circuit is programmed by the local processor to control the transfer of data between the external CPUs and the memory buffers.
Two interface circuits are coupled between the external CPUs and the memory buffers to provide two data paths for transferring data between the external CPUs and the memory buffers.
The data path control circuit contains two independent sequencing circuits for selecting memory buffers.
This allows one data path to be used for reading or writing to a number of the memory buffers while the other data path is simultaneously used for a different operation for the rest of the memory buffers.
The use of two interface circuits and the data path control circuit allows the system to write into some of the memory buffers and read from other memory buffers simultaneously over the two data paths; or one interface circuit can be used to read or write while the other is inactive, and vice-versa; or one interface circuit can be used to read while the other interface circuit is used to write, and vice-versa.
A dedicated logic circuit allows only one interface circuit to communicate with a specific memory buffer at any given time.
So, while one interface circuit is communicating to a specific memory buffer, the other interface circuit can communicate with any of the remaining memory buffers.
The local processor and the data path control circuit allow the data transferred between the external CPUs and the memory storage system to be stored or retrieved in a predetermined selective sequence.
Each memory buffer has a temporary memory (typically, a static ram) for temporarily storing data transferred to or from the memory storage element (typically, a disk drive)



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