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| Four quadrant multiplying divider using three log circuits |
| OF THE INVENTION Referring to the figures and more particularly FIG. 1 (prior art), the circuitry ... |
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| Method and apparatus for electro-optically convoluting a one-dimensional signal |
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| Exponential operation device |
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| Hardware arrangement for floating-point addition and subtraction |
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| Time reversal gaussian approximation filter |
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Microprocessor system having instruction cache with reserved branch target section
| Details |
Inventors: Dockser, Kenneth A.;
Assignee: VLSI Technology, Inc. (San Jose, CA)
Primary Examiner: Bowler; Alyssa H.
Assistant Examiner: Odedra; Dhiren R.
Attorney, Agent or Firm: Anderson; Clifton L.
A Harvard architecture data processing system includes a processor, main memory, an instruction cache, and a data cache. As is generally known with the Harvard architecture, these components are interconnected by an instruction bus, an instruction address bus, a data bus, and a data address bus. The instruction cache includes a branch target section and a general instruction section. For each instruction request by the processor, both sections are examined to determine if the requested instruction is in the cache. If it is, it is transmitted from the cache to the processor. If it is not, an instruction line including the requested instruction is fetched from main memory. If the requested instruction represents a jump (the result of an unconditional branch or a conditional branch the condition of which is met) the fetched instruction line can be stored only in the branch target section. If the requested instruction is simply the one located at the address one above that of the previous instruction, the fetched instruction line can only be stored in the general instruction section. This approach preserves branch targets in cache, while allowing all cached instructions to be available to the processor irrespective of whether a jump is called for. |
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DETAILED DESCRIPTION In accordance with the present invention, a computer system includes an instruction cache that includes both general instruction and branch target sections.
When a processor requests an instruction, both sections are checked for its presence.
However, an item from main memory can be stored in the branch target section only if it is the target of a branch instruction.
Accordingly, branch targets can be protected from overwrite by instructions that are not branch targets, while remaining available to the processor when called for even in the absence of a branch instruction.
A data processing system includes a central processor, main memory, a cache for storing instructions, and buses for conveying addresses, instructions, and data among these components.
The cache includes cache memory, a cache hit detector, cache logic for governing cache entries, and router means to select between the cache and main memory as the source for instructions.
In addition, the data processing system includes a branch detector that can be a separate component or part of the processor or the cache.
The cache logic is responsive to the branch detection signal.
If an instruction calls for a branch and the target of the branch is not in the cache, the cache logic enables the branch target section to consider the target instruction from main memory as a replacement for an existing entry.
(In general, the target instruction will be fetched as part of a "target" line of instructions having consecutive addresses in main memory.
Accordingly, when reference is made herein to an instruction fetched from main memory and stored in the cache, it is implicit that the instruction is transferred as part of an incorporating line of one or more instructions.
) The cache logic concurrently disables the general instruction section so that the branch target from main memory is not considered for entry therein.
If no branch is called for and the requested instruction is not in the cache, the general instruction section is enabled and the branch target section is disabled
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