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Multiple array customizable logic device
| Details |
Inventors: Agrawal, Om;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Callahan; Timothy P.
Attorney, Agent or Firm: King; Patrick T., Haynes; Mark A.
An integrated circuit having multiple programmable arrays in which a first programmable array receives a plurality of first inputs and generates a plurality of first outputs as programmed by the user. Also, a second programmable array receives a plurality of second inputs and generates a plurality of second outputs as programmed by the user. Also, buried state registers store signals as programmed by the user. An input multiplexer selects and supplies the first and second inputs from a variety of sources, including the first and second outputs, the buried state registers and I/O pins. An output multiplexer selects and supplies output signals to a set of output pins from a variety of sources, including the first and second outputs and the buried state registers. |
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DETAILED DESCRIPTION The present invention provides an integrated circuit having customizable logic, comprising a first programmable array means for receiving a plurality of first input terms and generating a plurality of first output terms as programmed by the user, and a second programmable array means for receiving a plurality of second input terms and generating a plurality of second output terms as programmed by the user.
Also included is a means for selectively interconnecting the plurality of first input terms, the plurality of first output terms, the plurality of second input terms and the plurality of second output terms, whereby the architecture of the integrated circuit having customizable logic can be adapted to suit the needs of a particular logic circuit.
In particular, the first programmable array means and the second programmable array means may be configured in series, in parallel, or in a combination of series and parallel as suits the needs of the user.
In another apsect, the present invention includes a plurality of buried state registers, responsive to at least a subset of the plurality of first output terms and plurality of second output terms, for providing stored signals that are available for use as input terms and/or output terms.
The means for selectively interconnecting the input and output terms includes in a preferred embodiment an input multiplexing means, responsive to an input select signal, for supplying as the plurality of first input terms or as the plurality of second input terms, a subset of signals selected from a plurality of signals, the plurality of signals selectable including a set of signals selected from the plurality of first input terms, the plurality of second input terms, the plurality of first output terms, and the plurality of second output terms.
Also, the means for selectively interconnecting includes an output multiplexing means, responsive to an output select signal, for supplying as output signals a subset of signals selected from a plurality of signals, the plurality of signals selectable as output signals including a set of signals selected from the plurality of first output terms and the plurality of second output terms
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