Multiple processor synchronized halt test arrangement

DETAILED DESCRIPTION An object of this invention is to provide a stable testing and debugging environment for a multiprocessor system and the ability to examine one or all processors when one or more halts.
The latter aids debugging of the total system.
A specific object is to provide an external mechanism for controlling a synchronization of the pausing/resuming of the processors operations.
Such a mechanism provides for: 1.
A stopping (pausing) of one processor in the multiprocessor system and a resultant stopping (pausing) of the remaining processors.
2.
A storage, or saving, of the current system state of each subsystem when the processors are paused.
3.
A means to display and modify the memory and registers of each subsystem while they are paused.
4.
Ensuring that system real time essentially stops so that real time dependent activities and processes are not affected.
5.
A means to restart all subsystems only if none is stopped (paused), and to restore the state of each subsystem (and to restart (resume) system execution as if no time had elapsed).
6.
A means for allowing some subsystems to only assert the pause/resume conditions, only for some subsystems to receive the pause/resume conditions, and for allowing some subsystems to both assert and receive the pause/resume conditions.
The foregoing objects are achieved in accordance with principles of an exemplary embodiment which comprises an arrangement referred to herein as Subsystem Synchronization.
The latter is a combination of hardware and software facilities which effect a coordinated simultaneous pausing/resuming of a plurality of the subsystems advantageously without inducing any unwarranted recovery actions or causing any real time or communication problems.
Specifically, the hardware structure of the Subsystem Synchronization illustratively comprises a circuit external to the multiprocessor subsystems for providing pause/resume interface control signals to and from subsystems.
The external circuit is responsive to a pause/resume signal from any subsystem by applying a pause/resume signal to all of the other processor subsystems of the multiprocessor system and thereby to preclude any undesired fault recovery operations of the system