Neighbor image processing device

DETAILED DESCRIPTION According to the present invention, the neighbor image processing device for processing image data according to a predetermined program is provided to achieve the foregoing objects and advantages.
The device comprises address generating means for simultaneously generating addresses corresponding to each of a central point and a plurality of individual neighbor points of an image neighbor region; buffer memory means for simultaneously receiving data on the points, and their corresponding addresses from the address generating means; central processor means coupled to the address generating means and the buffer memory means for comparing the neighbor point data with data on the central point of the neighbor region; arithmetic and logic means connected to the central processor means for selectively modifying the data simultaneously for the individual points according to instructions from the central processor means; data integration means for receiving a plurality of simultaneous outputs from the arithmetic and logic means and generating a single output based on instructions from the program; and decision integrating means for receiving a plurality of the single outputs from the data integration means and generating a coded multivalue based on instructions from the program.
Preferably the address generating means includes a first array of adders.
It is also preferred that the data integrating means include a second array of adders The second array may be tree shaped.
It is preferred that the buffer means include a plurality of individual buffer memories, and the arithmetic and logic means include a plurality of corresponding individual arithmetic units, one arithmetic unit being connected to each of the buffer memories Each buffer memory may comprise a high speed cache memory.
In addition, each arithmetic unit may include a transistor-to-transistor logic circuit The central processor means may include an arithmetic and logic unit having a transistor-to-transistor logic circuit therein