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Details
Inventors: Ogura, Naoyuki;
Assignee: Nec Corporation (Tokyo, JP)
Primary Examiner: Nelms; David C.
Assistant Examiner: Nguyen; Hien
Attorney, Agent or Firm: Foley & Lardner

A memory has a plurality of word lines WL1-8, a plurality of bit lines BL1-512 and BLa1-32, a plurality of memory cells C1-512 and Ca1-32, each of memory cells C1-512 and Ca1-32 are connected between selected one of said word lines WL1-8 and selected one of said bit lines BL1-512 and BLa1-32, said plurality of memory cells C1-512 and Ca1-32 connected to said selected one of said word lines WL1-8 are divided into a first group memory cells C1-512 and a second group memory cells Ca1-32,said first group memory cells C1-512 are provided for storing data and said second group memory cells Ca1-32 are provided for storing attribute data of said first group memory cells C1-512.

DETAILED DESCRIPTION To achieve the above mentioned object, a memory according to the present invention comprises a plurality of word lines, a plurality of bit lines, and a plurality of memory cells.
Each of the memory cells are connected between selected ones of the word lines and selected ones of the bit lines, and the plurality of memory cells connected to the selected ones of the word lines are divided into a first group memory cells and a second group memory cells.
The first group of memory cells are provided for storing data and the second group of memory cells are provided for storing attribute data of the first group memory cells.
Further, the present invention includes at least one sector (sector is defined as one word line) where sector data of a first byte number and attribute data of a second byte number corresponding to the sector data, are stored as one set of data in one row (column) or rows (columns), and are arranged, whereby an error correcting circuit in respect of data of one sector can be constituted by a circuit correcting error of one bit or bits.
Therefore, a bit line failure and a memory cell failure can be relieved by the error correcting circuit whereby the manufacturing yield is promoted and the manufacturing cost can be reduced.
Further, calculation of addresses for accessing to the attribute data is dispensed with, the number of rows (the number of columns) of one sector can significantly be decreased (minimum 1 row, 1 column) and the sector data and the attribute data can continuously be accessed thereby providing an effect by which the operational speed can be accelerated.



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