On chip buffering for optimizing performance of a bubble memory

DETAILED DESCRIPTION According to the present invention the magnetic domain memory architecture comprises a plurality of main storage loops disposed between a write-in section and a read-out section.
In the write-in section, the write-in means comprises a means for generating bits (domains or voids) and propagating said bits onto an input track position adjacent short or buffer storage loops and gate means for transferring said bits into and out of the buffer storage loops as a block of data bits, an idler to receive and hold said block of data bits transferred from the buffer loops and transfer-in gate means for transferring said block of bits received from the idler to the main storage loops.
In the read-out section, the read-out means comprises transfer-out gate means for transferring blocks of data bits from the main storage loops, an annihilator and a second idler to receive the transferred-out block of bits not annihilated and transfer-in gate means for transferring the block of bits from the idler into a second set of buffer loops, transfer-out gate means for transferring a block of data bits from said buffer loops onto an output track to which is connected a sensor for detecting domains serially.
The read-out section may also possibly include a replicator.