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On chip monitor
| Details |
Inventors: Mercy, Brian R.;
Assignee: IBM Corporation (Armonk, NY)
Primary Examiner: Zache; Raulfe B.
Assistant Examiner:
Attorney, Agent or Firm: Hoel; John E.
Level sensitive scan design (LSSD) scan strings on an integrated digital logic circuit chip are employed for multiple functions of providing control parameters to logic blocks on the integrated circuit chip, and for providing reconfiguration messages to reconfiguration logic on the integrated circuit chip, in addition to the normal function of transferring test data to various portions of the integrated circuit chip. This reduces the number of input/output pads on the integrated circuit chip which must be dedicated to these functions. |
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DETAILED DESCRIPTION Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 1.
In an integrated digital logic circuit chip having an LSSD serial input line, an LSSD serial output line, N digital input lines and a logic block thereon, comprising: a control parameter shift register having a serial input connected to said LSSD serial input line, a parallel output connected to a control input of said logic block, and a serial output, for providing control parameters to said logic block during a first interval; an LSSD shift register having a parallel input connected to said N digital input lines, a serial input connected to said serial output of said control parameter shift register, and a parallel output connected to a data input of said logic block, for selectively transferring operand data from said N digital input lines to said data input of said logic block during a second interval or alternately for transferring test data from said serial input line to said data input of said logic block during a third interval; whereby a single LSSD scan string can be used for both control functions and testing functions.
2.
In an integrated digital logic circuit chip having an LSSD serial input line, an LSSD serial output line, N digital input lines and a logic block thereon, comprising: an LSSD shift register having a parallel input connected to the output of said logic block, a serial input connected to said serial input line and a parallel output and a serial output line, for selectively transferring operand data from said logic block to said parallel output during a first interval or alternately for transferring test data from said logic block to said serial output line during a second interval; a control parameter shift register having a serial input connected to said serial output of said LSSD shift register, a parallel output connected to a control input of said logic block, and a serial output connected to said LSSD serial output line, for providing control parameters to said logic block during a third interval; whereby a single LSSD scan string can be used for both control functions and testing functions
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