Output logic macrocell with enhanced functional capabilities

DETAILED DESCRIPTION This invention provides an output logic macrocell for use with a logic block such as a programmable logic array.
The output logic macrocell contains an XOR gate, an OR gate, a register, and a plurality of multiplexers connected up in such a way as to provide enhanced functional capabilities to the programmer, including cascaded XOR gates, function sharing with another OLMC, and asynchronous register control and clocking.
In addition, inputs of a plurality of OLMC's are linked to the product terms and other outputs of the logic block through a product term allocation array, thereby allowing maximum flexibility in the distribution of the outputs of the logic block to the respective OLMC's and allowing the performance of extremely complex functions.
One of the multiplexers in each OLMC has an output connected to an input of the XOR gate.
One input of this multiplexer is connected to ground.
When the grounded input is selected, the XOR gate simply passes the signal appearing at its other input.
In effect, the XOR gate is taken out of the circuit.
The OLMC also includes a bypass path which bypasses the XOR and OR gates and thereby provides extremely fast performance.
The OLMC provides either a registered or an combinatorial output.
In another aspect of this invention, a logic block is used to generate a clock pulse.
The output of the logic block "clock" is connected to the global clock distribution system of this high density programmable logic device, as well as to input/output cell clocks in the device.
This invention will be more fully understood in conjunction with the following detailed description taken together with the drawings.