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| Transition for electrical apparatus |
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| Microprogram control system |
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| Data bank priority system |
| OF THE PREFERRED EMBODIMENT Turning now to the drawings, there is shown in FIG. 1 part of a data ... |
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| Integrated circuit device having a memory and majority logic |
| I claim: 1. An integrated circuit device comprising: a memory having at least first, second and ... |
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| Logic circuit system with latch circuits for reliable scan-path testing |
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| Optional single or double clocked latch |
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Power-up circuit for field programmable gate arrays
| Details |
|
Inventors: Apland, James M.; Chan, Andrew K.;
Assignee: QuickLogic Corporation (Sunnyvale, CA)
Primary Examiner: Leja; Ronald W.
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill, MacPherson, Franklin and Friel, Wallace; T. Lester
A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input. |
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DETAILED DESCRIPTION FIG.
1 is an illustration of a portion of a prior art device 100 showing a first logic module 101 and a second logic module 102 that have been interconnected by programmed antifuses 104 and routing conductors 106.
Details of such a prior art device can be found in U.
S.
patent application Ser.
No.
08/667,702, which is incorporated herein in its entirety.
Details of antifuses can be found in U.
S.
Pat.
Nos.
5,302,546, 5,294,846, and 5,243,226 all of which are incorporated herein in their entirety.
The output of logic module 101 includes inverter 108, protection transistor 110 that has a gate connected to a voltage generated by a charge pump, V.
sub.
CP 112, and protection transistor 114 that has a gate connected to the supply voltage, V.
sub.
CC 115.
The logic module 102 includes a NAND gate 116 having seven inputs (three are noninverting and four are inverting).
Each of the top six inputs can be selectively connected to logic modules via the interconnect structure.
One of the inputs to the NAND gate 116 is an internal disable input INTDIS 120 that is used in the prior art to disable the NAND gate 116 during testing of the device.
NAND gate 116 is disabled by supplying a digital logic HIGH to the internal disable input INTDIS 120.
During power up, the internal disable input INTDIS 120 is supplied with a digital logic LOW in the prior art device.
FIG.
2 is a transistor level diagram of NAND gate 116 showing the seven inputs which have been numbered from 1 to 7 and the NAND gate output 200.
As discussed in conjunction with FIG.
1, each of the six inputs 1 through 6 can be connected to other logic modules (such as logic module 101) via the interconnect structure.
The seventh input 7 (also labeled 120) is the internal disable input INTDIS.
The input 1 is connected to the gate of the nmos transistor 202 and to the gate of the pmos transistor 204.
The input 2 is connected to the gate of the nmos transistor 206 and to the gate of the pmos transistor 208.
The input 3 is connected to the gate of the nmos transistor 210 and to the gate of the pmos transistor 212
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CPUs 
