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Details
Inventors: Norman, Kevin A.;
Assignee: Altera Corporation (Santa Clara, CA)
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Rosenblum, Parish & Bacigalupi

A programmable integrated circuit micro-sequencer apparatus including a dynamically programmable logic device (DPLD) combined with an EPROM look-up table to form a novel look-up table programmable logic device (LTPLD) which is combined with a register to form a stand alone micro-sequencer (SAM) that may be used to implement state machines and microcoded controller devices. The usefulness of the present invention is further expanded by the addition, in various other embodiments, of code look-up tables, priority encoders, multiplexors, stacks and counters and all associated control circuits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred implementation of the basic building block of the present invention, the Dynamically Programmable Logic Device (DPLD), is generally illustrated in FIG.
3.
Comparing this figure with FIG.
2.
It will be noted that the EPROM transistor 220 forming each erasable programmable cell 221 of the prior art circuit has been replaced by a series connected pair of N-channel transistors 320 and 322 forming a dynamically reprogrammable cell 321.
Otherwise the structure of the first NOR gates 202 and 302 are essentially the same.
The series pair of transistors 321 consists of a first transistor 320 with the same gate connection as the corresponding EPROM transistor 220 in FIG.
2.
The gate connection of the second transistor in 322 is connected to one of the "programming" signal inputs 308.
Whereas the programming in FIG.
2 is contained in the floating gate of the EPROM transistor 220, in FIG.
3 the programming is dynamic and enters the circuit through the programming leads or terminals 308.
A similar correspondence exists in the cells 324 of the second level NOR gates where the dynamic programming of the second level transistor 325 enters the DPLD through programming leads or terminals 310.
The input circuits 200 and 300 and the output circuits 206 and 306 are identical in both embodiments.
It will thus be appreciated that, whereas in the prior art circuit of FIG.
2, the logical function to be implemented by the circuit was predetermined when the device was programmed, the programming of the DPLD of the present invention is dynamic.
That is, it can be changed and redefined as often as once during each clock cycle of operation of the device.
In FIG.
3a one possible source of the dynamic programming signals to a DPLD is illustrated.
In this preferred embodiment the source is an EPROM 316 of conventional design, although other sorts of memory including, but not limited to, ROM, RAM, EEPROM, and FUSE array device, would also serve this function



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