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 Programmable logic array intergrated circuit devices

Details
Inventors: Cliff, Richard G.; Reddy, Srinivas T.; Jefferson, David E.; Raman, Rina; Cope, L. Todd; Lane, Christopher F.; Huang, Joseph; Heile, Francis B.; Pedersen, Bruce B.; Mendel, David W.; Lytle, Craig S.; Bielby, Robert R. N.; Veenstra, Kerry;
Assignee: Altera Corporation (San Jose, CA)
Primary Examiner: Santamauro; Jon
Assistant Examiner:
Attorney, Agent or Firm: Fish & Neave, Jackson; Robert R., Beninati; John

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

DETAILED DESCRIPTION These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit devices having the traditional two-dimensional array of programmable logic regions with horizontal conductors associated with each row and vertical conductors associated with each column, but with the difference that some of the horizontal conductors associated with each row extend continuously or substantially continuously along only approximately half the length of the row.
Thus each row is divided into two mutually exclusive halves, with some "half-horizontal" conductors extending along each of the two halves.
In this way a half-horizontal conductor can be used to make connections to, from, and/or between logic regions in a half of the row without having to use a much longer than necessary full-horizontal conductor for this purpose.
The full-horizontal conductors (which extend continuously or substantially continuously along the entire length of a row, and which are sometimes also referred to as global horizontal conductors) can be saved for signals that must be transmitted beyond either half of the row.
Because two end-to-end half-horizontal conductors occupy the same space as one full-horizontal conductor, the provision of half-horizontal conductors makes more efficient use of the horizontal conductor real estate on the chip.
In particular, the half-horizontal conductors allow the number of full-horizontal conductors to be reduced.
Reducing the number of horizontal conductors also helps reduce the size of the programmable switch arrays used to programmably connect the horizontal conductors to the inputs of each logic region.
Axially aligned and adjacent half-horizontal conductors are preferably not directly connectable to one another.
Thus there is preferably no possibility of programmably optionally piecing together axially aligned half-horizontal conductors to make longer horizontal conductors.
Instead, that longer horizontal conductor resource is the global horizontal conductors, which are preferably continuous or substantially continuous and not made up of pieced-together shorter conductors



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