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Programmable logic cell and array
| Details |
Inventors: Furtek, Frederick C.;
Assignee: Concurrent Logic, Inc. (Sunnyvale, CA); Apple Computer, Inc. (Cupertino, CA)
Primary Examiner: Hudspeth; David
Assistant Examiner:
Attorney, Agent or Firm: Pennie & Edmonds
A logic cell is described having four inputs, four outputs, a control store, means for multiplexing the four inputs onto two leads and logic means that operate in response to the signals on the two leads and signals from the control store to product output signals which are applied to the four outputs. Illustrative logic functions provided by the logic means include a cross-over or identity function, a change in the routing direction of an input signal, NAND and XOR gates and a D-type flip-flop. The selection of two of the four inputs as well as the selection of the particular logic function that is implemented is controlled by control bits stored in the control store. Numerous such logic cells are arranged in a two-dimensional matrix such that each cell has four nearest neighbor cells, one to its left (or to the West) one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each one of the four inputs to a logic cell comes from a different one of that cell's four nearest neighbors and similarly each one of a cell's outputs is provided to a different one of that cell's four nearest neighbors. As a result of this arrangement, individual cells can be combined to produce blocks of cells that implement all manner of functions. |
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DETAILED DESCRIPTION OF DRAWING FIG.
1 depicts an array 10 of cells 20 formed in accordance with the present invention.
As is apparent, the cells are arranged in a two dimensional matrix with each cell having four nearest neighbors, one to its left (or to the West) one to its right (or to the East), one above it (or to the North) and one below it (or to the South).
Each one of cells 20 has four inputs 22a, 23a, 22b, 23b and four outputs 24a, 25a, 24b, 25b.
Each of the four inputs of a cell is connected to one of the outputs of a different one of that cell's four nearest neighbor cells; and each of the four outputs of a cell is connected to an input of a different one of that cell's four nearest neighbor cells.
In addition to the inputs shown in FIG.
1 each cell also has a global-clock input and control-signal inputs.
Close examination of FIG.
1 will reveal that there are differences among the cells relating to the orientation of their inputs and outputs.
For example, in some cells, both inputs 22a, 23a are located in the upper left corner, in others in the bottom right corner.
In still other cells, one input is to one corner while the other is to the diametrically opposite corner.
In all, there are four different orientations of the inputs and outputs which are depicted in cells 20A, 20B, 20C, 20D of FIGS.
1 and 2A-2D.
As will be apparent, each of cells 20A, 20B, 20C, 20D is symmetric about a northeast-southwest or a northwest-southeast axis of symmetry.
This use of four different cell orientations is to be contrasted with prior art cells such as those described by Manning in which each cell in an array is identical and has the same orientation in the array.
In such prior art cells, the effect of different orientations of the cells can only be achieved at the expense of increased state storage, increased decoding logic, increased switching logic, increased processing logic and increased wiring, all of which result in cells having larger physical size and slower switching speed.
In an illustrative embodiment of cell 20 as shown in FIG
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