Programmable multiplexing input/output port

DETAILED DESCRIPTION The present invention discloses an input/output buffer design for FPGAs and other programmable devices.
An output buffer of the present invention multiplexes a selection of internal signals onto a single wire.
An input buffer of the present invention demultiplexes such signals for utilization within the programmable device.
A multiplexing output buffer comprises a means for selecting a portion of the internal device signals for multiplexing, a multiplexor and a buffer for driving the multiplexed signals onto the device pin.
The control logic for the multiplexor may be either internal or external to the programmable device.
If the control is internal, it may be created either by the programmable logic array or by dedicated hardware.
A multiplexing input buffer comprises an input buffer for receiving the multiplexed signal from the pin, a demultiplexor and means for driving the demultiplexed signals into the programmable device.
The control logic for the demultiplexor may be either internal or external to the programmable device.
If the control is internal, it may be created either by the programmable logic array or by dedicated hardware.
A buffer hardware may comprise either a multiplexing input buffer, a multiplexing output buffer or both.
In addition, the buffer hardware may also comprise the conventional programmable pin circuit of the underlying programmable device.
The device is then programmed to select the proper buffer form.