 Tile-based modular routing resources for high density programmable logic device |
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| Programmable logic array integrated circuits |
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| Electric socket adapter |
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| Memory arbitration between timekeeping circuitry and general purpose computer |
| It is, therefore, an object of this invention to provide a method and circuitry for arbitrating ... |
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| Transition for electrical apparatus |
| I claim: 1. An electrical transition comprising: a) a nonconductive base having extending upwardly ... |
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| Microprogram control system |
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| Data bank priority system |
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| Integrated circuit device having a memory and majority logic |
| I claim: 1. An integrated circuit device comprising: a memory having at least first, second and ... |
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Programming architecture for a programmable integrated circuit employing antifuses
| Details |
Inventors: Kolze, Paige A.;
Assignee: QuickLogic Corporation (Sunnyvale, CA)
Primary Examiner: Hudspeth; David R.
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill,MacPherson, Franklin and Friel, Wallace; T. Lester
A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. In one aspect, the number of programming conductors and the number of perpendicular programming control conductors for a logic module are substantially equal. In another aspect, programming current is supplied onto long routing wire segments via two programming transistors and two programming conductors. In another aspect, a pattern of programming drivers alternates from one side of the integrated circuit to the opposite side from one column of macrocells to the next. In other aspects, control conductors and programming conductors are tested with test antifuses and test transistors. In another aspect, adjacent logic modules have mirrored structures so that they can share an intervening programming conductor resource. In another aspect, L-shaped programming power busses are provided and in another aspect, an express wire is simultaneously driven with programming current from two different programming voltage terminals. In other aspects, a test circuit tests the integrity of collinear routing wire segments and output programming transistors are tested. In another aspect, antifuses on branches of clock conductors are programmed. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
1 is a diagram showing how FIGS.
1A, 1Ba, 1Bb, 1Bc, 1C, 1D, 1E, 1Fa, 1Fb, 1Fc, 1G, 1H, 1I, 1Ja, 1Jb, 1Jc, 1K, 1L, 1M, 1Na, 1Nb, 1Nc, 1O and 1P fit together to form one large simplified schematic of one embodiment of a programming structure of a programmable integrated circuit employing antifuses.
The boxes of FIG.
1 each have a letter to indicate one of the FIGS.
1A-1P.
The "A" in the upper left box, for example, indicates FIG.
1A.
As is seen from FIG.
1, the structure of FIG.
1A borders FIG.
1B on the right and the structure of FIG.
1E on the bottom.
Although two structures of FIG.
1B are disposed between the structures of FIG.
1A and 1C and two structures of FIG.
1B are disposed between the structures of FIG.
1C and 1D in the composite schematic, it is to be understood that additional structures of FIGS.
1B could be provided to make a wider integrated circuit.
Similarly, additional structures of FIGS.
1F could be provided between the structures of FIG.
1B and FIG.
1J to increase the height of the integrated circuit.
A repeated portion of the integrated circuit including a module of logic elements and a portion of the programmable interconnect and its programming structure (such as the structure of FIG.
1F) is called a "macrocell".
Various aspects of the programmable integrated circuit of FIG.
1 are set forth below in further detail.
The microfiche appendix includes a complete hierarchical schematic (including test circuitry) of the programmable integrated circuit of FIG.
1.
The subject matter of copending application Ser.
No.
08/667,783 filed Jun.
21, 1996 ("Interface Cell For A Programmable Integrated Circuit Employing Antifuses" by Kolze et al.
) which describes an interface cell of FIG.
1, is hereby incorporated herein by reference.
FIG.
2 is a simplified diagram illustrating a first aspect in accordance with the embodiment of FIG.
1.
In FIG.
2, the "X" symbols represent antifuses called cross antifuses.
See U.
S.
Pat.
No.
5,424,655 (the subject matter of which is incorporated herein by reference) for background information
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