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Pulse-to-static conversion latch with a self-timed control circuit
| Details |
Inventors: Chappell, Terry Ivan; Henkels, Walter Harvey; Hwang, Wei; Joshi, Rajiv Vasant;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Lam; Tuan T.
Assistant Examiner:
Attorney, Agent or Firm: F. Chau & Associates, LLP
A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide circuit techniques for interfacing dynamic and static circuits via a latch.
It is another object of the invention to provide self-timed clock generators for controlling the evaluation, resetting, and write-enable functions of the latch.
It is a further object that the self-timed clock generators have only a single active control input in normal operation.
This input is the system clock.
It is a further object to provide a dynamic-to-static conversion latch that has a pulse-catching input and a static output.
It is a further object that the latch be relatively simple in design and provide fast and effective pulse-to-static conversion of digital signals.
It is a further object to employ dynamic circuit techniques to achieve a pulse-to-static latch having high speed, low power, and a small area.
It is a further object that the circuitry be fully compatible with the Level Sensitive Scan Design (LSSD) test-methodology and be compatible with the self-resetting CMOS test-methodology.
According to the invention, the problems encountered in conventional mixed dynamic/static approaches are addressed by implementing the pulse-to-static conversion latch-array consisting of an n-bit latch-array and a self-timed control macro, which utilizes self-resetting CMOS circuit techniques.
With the self-timed concept, the control macro requires only one control-input, the system clock.
The evaluation, resetting and write-enable signals are all generated internally, within the contro macro.
The design is fully compatible with the LSSD test methodology, and with self-resetting CMOS diagnostic modes.
By employing self-resetting CMOS circuit techniques, the pulse-to-static conversion latch array of the present invention provides high performance, low power, pulse-to-static conversion, thereby enabling fast-cycle-time, minimum-delay-time and low-latency designs.
Thus the latches make possible synchronization, pipelined operations and LSSD-testing in advanced high clock rate digital systems
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